L21-ac-pipeliningI-6up

L21-ac-pipeliningI-6up - CS61C L21 Pipelining I (1) Chae,...

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Unformatted text preview: CS61C L21 Pipelining I (1) Chae, Summer 2008 UCB Albert Chae, Instructor inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures Lecture #21 Pipelining I 2008-7-28 Minesweeper circuits http://www.claymath.org/Popular_Lectures/Minesweeper/ http://for.mat.bham.ac.uk/R.W.Kaye/minesw/ASE2003.pdf CS61C L21 Pipelining I (2) Chae, Summer 2008 UCB 5 steps to design a processor 1. Analyze instruction set datapath requirements 2. Select set of datapath components & establish clock methodology 3. Assemble datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Assemble the control logic Control is the hard part MIPS makes that easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates Review: Single cycle datapath Control Datapath Memory Processor Input Output CS61C L21 Pipelining I (3) Chae, Summer 2008 UCB RegDst = add + sub ALUSrc= ori + lw + sw MemtoReg = lw RegWrite = add + sub + ori + lw MemWrite = sw nPCsel = beq Jump = jump ExtOp = lw + sw ALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR) ALUctr[1] = or where, rtype = ~op 5 ~op 4 ~op 3 ~op 2 ~op 1 ~op , ori = ~op 5 ~op 4 op 3 op 2 ~op 1 op lw = op 5 ~op 4 ~op 3 ~op 2 op 1 op sw = op 5 ~op 4 op 3 ~op 2 op 1 op beq = ~op 5 ~op 4 ~op 3 op 2 ~op 1 ~op jump = ~op 5 ~op 4 ~op 3 ~op 2 op 1 ~op add = rtype func 5 ~func 4 ~func 3 ~func 2 ~func 1 ~func sub = rtype func 5 ~func 4 ~func 3 ~func 2 func 1 ~func With control breaking apart code to run on the datapath , what does this mean? add sub ori lw sw beq jump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr[0] ALUctr[1] AND logic OR logic opcode func How We Build The Controller CS61C L21 Pipelining I (4) Chae, Summer 2008 UCB lw $t0, 0($2) lw $t1, 4($2) sw $t1, 0($2) sw $t0, 4($2) High Level Language Program (e.g., C) Assembly Language Program (e.g.,MIPS) Machine Language Program (MIPS) Hardware Architecture Description (e.g., block diagrams) Compiler Assembler Machine Interpretation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Logic Circuit Description (Circuit Schematic Diagrams) Architecture Implementation Call home, we ve made HW/SW contact! CS61C L21 Pipelining I (5) Chae, Summer 2008 UCB An Abstract View of the Critical Path Critical Path (Load Instruction) = Delay clock through PC (FFs) + Instruction Memorys Access Time + Register Files Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write...
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L21-ac-pipeliningI-6up - CS61C L21 Pipelining I (1) Chae,...

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