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lec2 - Announcements Labs to Start in 2 Weeks HW#1 Due in 1...

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1 Announcements Labs to Start in 2 Weeks HW#1 Due in 1 Week 2 ECE 406: Design of Complex Digital Systems ECE 406: Design of Complex Digital Systems Lecture 2 Verilog Syntax Verilog Syntax Fall 2008 Xun Liu Xun Liu NC State University 3 Why Verilog? Most commonly used in the US semiconductor industry Supported by all commercial tools Least verbose Fast simulation 4 Verilog Language Conventions Verilog code contains a stream of “tokens”. Tokens can be comments, delimiters, numbers, strings, identifiers and keywords . Case sensitive: Keywords are in lowercase. Whitespace: Blank spaces, tabs and newlines are ignored. Exceptions are when it separates tokens or when it appears in strings. Statement terminator: Most Verilog statements end with a semicolon. Comments: 1) Single Line “ // ” 2) Multi-Line (cannot be nested): “ /* */
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