Lec2 - Announcements Labs to Start in 2 Weeks HW#1 Due in 1 Week ECE 406 Design of Complex Digital Systems Lecture 2 Verilog Syntax Fall 2008 Xun

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1 Announcements § Labs to Start in 2 Weeks § HW#1 Due in 1 Week 2 ECE 406: Design of Complex Digital Systems ECE 406: Design of Complex Digital Systems Lecture 2 Verilog Syntax Verilog Syntax Fall 2008 Xun Liu Xun Liu NC State University 3 Why Verilog? § Most commonly used in the US semiconductor industry § Supported by all commercial tools § Least verbose § Fast simulation 4 Verilog Language Conventions § Verilog code contains a stream of “tokens”. § Tokens can be comments, delimiters, numbers, strings, identifiers and keywords . § Case sensitive: Keywords are in lowercase. § Whitespace: Blank spaces, tabs and newlines are ignored. Exceptions are when it separates tokens or when it appears in strings. § Statement terminator: Most Verilog statements end with a semicolon. § Comments: 1) Single Line “ // ” 2) Multi-Line (cannot be nested): “ /* */
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5 Values Sized numbers : <size>’<base format><value> <size> : specifies number of bits in number (in decimal) <base format> : decimal (‘d, ‘D); hexadecimal (‘h, ‘H); binary (‘b, ‘B); octal (‘o, ‘O) <value> : digits (in base format) of the numeric value, “_” can be used for readability § Examples: You should always specify the size and base information, unless … 6 Special Values Verilog provides two special values, x and z . x denotes an unknown or undefined value. z denotes a “high impedance” value 7 Physical Meaning of Values 0 and 1 x 0 1 1 0 out in Why is “x” useful? 8 Physical Meaning of “Z” 1 1 0 enable 1 0 0 1 z - out in “tri-state inverter” Use when multiple gates drive the same net z enable in out
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9 Special Cases Zero fill / extension: High order unspecified bits are filled with zeros unless the most significant bit specified is an x or z , in which the x or z is left extended to fill the bit field.
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This note was uploaded on 12/07/2009 for the course ECE 406 taught by Professor Davis during the Spring '08 term at N.C. State.

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Lec2 - Announcements Labs to Start in 2 Weeks HW#1 Due in 1 Week ECE 406 Design of Complex Digital Systems Lecture 2 Verilog Syntax Fall 2008 Xun

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