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HW6Sol

# HW6Sol - EECE 321 Electronics-l(Spring 2007 University of...

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Unformatted text preview: EECE 321: Electronics-l (Spring 2007. University of New Mexico) Homework-Vi (Due Date: Monday. March 26"1 in class) Ken Gant 1) (a) Draw a CMOS logic circuit that implements the following truth table. Assume that inverted inputs are also available. (5 points) Hint: Draw the logic equation for the truth table and design the circuit with nMOS and pMOS transistors. HW6 Problem 1A X0: Vdd 1 0 DC 5 Va 2 0 DC 5 pulse {.1 4.95 D lns lns an 20ns) Vna 3 0 DC 5 pulse {4.95 .l 0 ins 1ns 9ns 20nsi Vb d 0 DC 5 pulse {0.05 4.9 0 ins lns 19n5 40ns) an 5 0 DC 5 pulse {4.9 0.05 0 lns lns 19n5 40n3} Mp1 6 2 I 1 pfet w=4u L=lu Mp2 6 5 1 1 pfet W=du L=lu Mp3 T d 6 6 pfet W=4u L=lu Mp4 ? 3 6 6 pfet W=4u L=lu Mnl ? 2 B 8 nfet w=2u L=lu Mn2 7 4 9 9 nfet W=2u L=lu Mn3 8 5 U 0 nfet W=2u L=1u MR4 B 3 0 0 nfet w=2u L=lu Hip 10 ? l l pfet W=2u L=lu Min 10 7 0 O nfet W=1u L=1u .model pfet pmos llevel=2 vto=-1J .model nfet nmos llevel=2 vto=1l Vtzjtred) is A, V(4](green) is B, Vflltblue) is the uninverted output;r and V[10)[magent (b) Repeat part a without using an output inverter ( 5points) V59 a) is the final output. FE F = “(A + !B)(!A+ 3)) ms Problem 13 Xor Vdd l 0 DC 5 Va 2 0 DC 0.1 pulse Vb 4 0 DC 0.05 pulse BC 4.9 pulse an Mp1 Mp2 Mp3 Mp4 Mnl MHZ Mn3 Mn4 .model pfet -model nfet mmmmmmumm Nmanhmwo DOWW‘JG‘I—‘H oomwumI—IH pfet pfet pfet pfet nfet nfet nfet nfet pmos nmos W=4u L=lu W=4u L=1u W=4u L=lu w=du L=lu W=2u L=lu W=2u L=lu w=2u L=lu W=2u LFlU {level=2 vto=—1 kp=le—4) (level=2 vto=1 kp=1e—4) {.l 4.95 U Ins Ins 9ns ZDns) Vna 3 0 DC 4.95 pulse [4.95 .1 0 lns lns 9n5 20n3) {0.05 4.9 U lns lns 19n3 40n3) {4.9 0.05 D lns lns 19n3 40n5) _-wa-ﬂn-un ﬁn \H2) is A, W4) is B, and VIIBJ is the final output. ...
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HW6Sol - EECE 321 Electronics-l(Spring 2007 University of...

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