49595

49595 - EE 541 Class Lecture Week 5 Design Issues for...

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EE 541 Class Lecture Week 5 Prof. John Choma, Professor Department of Electrical Engineering- Electrophysics University of Southern California University Park; MC: 0271; PHE #604 Los Angeles, California 90089-0271 213-740-4692 [USC Office] 213-740-7581 [USC Fax] johnc@usc.edu Design Issues for Operational Transconductors Fall 2006 Semester
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University of Southern California Choma: EE 541 80 Lecture Overview Lecture Overview z General Requirements ± High Input Impedance ± High Output Impedance ± Linearity ± High Unity Gain Frequency ± Linear Transconductance Dependence On Control Voltage Or Current z Architectures ± Transconductance Enhancement Cell (TEC) ± Composite Field Effect Transistor (COMFET) ± Examples Of Transconductor Cells z Low Voltage Biasing z Common Mode Feedback ± Establishment Of Output Port Biasing ± Minimization Of Offset ± Capacitive Loading Phenomena
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University of Southern California Choma: EE 541 81 + + V + V I o I o V o V o G m + V GV m Non-Phase Inverting Transconductor Cell I o V o V V + I o V o G m + V m Phase Inverting Transconductor Cell V c V c General Requirements General Requirements z Impedances ± Very Large At Both Input Ports ± Very Large At Output Port z Offset Voltages ± Quiescent Voltages Identical At Both Input Ports ± Quiescent Output Voltage Identical To Each Quiescent Input Voltage z Transfer Performance ± Output Current Is Linear Function Of Differential Input Voltage ± Large Unity Gain Frequency Of V o /V ± Transconductance Linearly Dependent On Control Voltage, V c
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University of Southern California Choma: EE 541 82 Transconductance enhancement cell (TEC) Transconductance enhancement cell (TEC) z Amplifier ± Simple Dominant Pole Structure ± Enhancement By (A o + 1) Factor ² Transconductance Of M1 ² Channel Resistance Of M1 ² Applicability ¾ Deep Submicron Devices ¾ Integrator Realization z Source ± Generally Norton Output Circuit Of Common Source Stage ± Y s = G s + sC s ± I ss Is Q-Point Current Of Stage ± I s Is Signal Output Current Of Stage z Load: Y l = G l + sC l z Biasing In Saturation Y s I s I ss I dd V ss I 1 V 1 V 2 A o + V + V Y l I 2 M1 +
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University of Southern California Choma: EE 541 83 + I 1 V 1 A o + V dd M1 I 2 I 2 V 2 V 2 gV m1 a o1 2 λ b m1 b g o1 g me + V b I 1 I 1 V 1 V 1 + a AV + o1 me 1 g o1 V 2 I 2 V a = - (A o +1)V 1 V b = - V 1 TEC Small Signal Model TEC Small Signal Model z Low Frequency Analysis z Only High Impedance Node Is Drain Of Transistor M1 ( ) () 12 m 1 a b 1 m 1 b o 1 1 2 12m e 1 o 1 2 me o1 o b1 m1 IIg V λ g V V II g V g V ggA 1 λ g =− + = ++ + ±
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University of Southern California Choma: EE 541 84 TEC Performance Metrics TEC Performance Metrics gV o1 2 g me I 1 V 1 me 1 g o1 V 2 I 2 Y s I s Y l Z in Z out ( ) om 1 me out o1 s o1 s A 1g g 1 Z1 gY g Y  +  =+≈  z Input Impedance (Very Low) z Output Impedance (Very High) z Current Gain z Excellent Current Buffer For A Cascode Application () o1 in me l 1 g 11 A =+ + me l l 2 s s me l out l out Y I 1 IY Y Y Y ≈≈ ++ +
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University of Southern California
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This note was uploaded on 12/12/2009 for the course EE 541 at USC.