IST4_lec18

IST4_lec18 - IST 4 Information and Logic IST 4: Planned...

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IST 4 Information and Logic
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1 M1 31 6 2 6 5 26 19 M2 5 4 12 4 5 3 M2 28 3 2 21 2 1 14 M1 7 fri thr wed tue mon IST 4: Planned Schedule – Spring 2008 x= hw#x out x= hw#x due = today T Mx= MQx out Mx= MQx due T MQ1 MQ2 students’ presentations
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Last Time Computing with Dynamic: Convergence in Neural Networks
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Feedback Networks Computing with Dynamics Feedback Network Input: initial state Output: stable state Associative Memory “The Leibniz-Boole Machine”
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Feedback Networks Computing with Dynamics Feedback Network Input: initial state Output: stable state Associative Memory “The Leibniz-Boole Machine”
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Feedback Networks Computing with Dynamics Feedback Network Input: initial state Output: stable state Associative Memory “The Leibniz-Boole Machine”
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The Three Cases 11 -11 -1-1 1-1 11 -11 -1-1 1-1 W mode symmetric antisymmetric serial fully-parallel 1 1,2 4 ? Cycle lengths 1 2 3 Example # 11 -11 -1-1 1-1 1 2 3
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The Three Cases of Covergence Cycle lengths W mode symmetric antisymmetric serial fully-parallel 1 1,2 4 ? 1 2 3 Example # 1 Hopfield 1982 2 Goles 1985 3 Goles 1986
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Questions on Convergence Cycle lengths W mode symmetric antisymmetric serial fully-parallel 1 1,2 4 ? 1 2 3 Example # 1 Hopfield 1982 2 Goles 1985 3 Goles 1986 Q1: Are the three cases “distinct”? Q2: Elementary proof? (wo/energy)
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An Inspiring Paper Warren McCulloch 1899 - 1969 Walter Pitts 1923 - 1969 Neurophysiologist, MD Their collaboration let to the 1943 seminal neural networks paper: A Logical Calculus of Ideas Immanent in Nervous Activity Logician, Autodidact Neural networks and Time Threshold Logic State Machines Logic Memory Feedback Networks
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Today State Machines Perspective and Summary
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State Machines - Definition
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/0 /0 /1 State Diagram a b 0 1 1 /1 0 states – labeled vertices transitions – directed edges inputs labels on edges that correspond to the symbols that trigger the transitions outputs labels on edges that correspond to the symbols that are generated by the transitions
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/0 /0 /1 a b 0 1 1 /1 0 State Diagram state machine symbols in symbols out
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/0 /0 /1 a b 0 1 1 /1 0 starting state 0 0 a State Diagram state machine
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/0 /0 /1 a b 0 1 1 /1 0 starting state 1 1 a b State Diagram state machine
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/0 /0 /1 a b 0 1 1 /1 0 starting state 1 0 b a State Diagram state machine
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/0 /0 /1 State Diagram for ??? a b 0 1 1 /1 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 starting state a a b b b a b b b b a a
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/0 /0 /1 State Diagram for XOR a b 0 1 1 /1 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 starting state a a b b b a b b b b a a XOR of the incoming sequence…. . output 1 if saw an odd number of 1’s even odd
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Q: How to implement it using a logic circuit ? /0 /0 /1 a b 0 1 1 /1 0 starting state even odd State Diagram for XOR
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An Architecture for a State Machine /0 /0 /1 a b 0 1 1 /1 0 starting state even odd logic circuit state inputs output functions of inputs and current state How do we represent a and b ?
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/0 /0 /1 a=0 b=1 0 1 1 /1 0 starting state even odd logic circuit state inputs output functions of inputs and current state An Architecture for a State Machine
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IST4_lec18 - IST 4 Information and Logic IST 4: Planned...

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