Sample final

Sample final - 6:. Probiem 1: Diode Circuit Analysis: (20...

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Unformatted text preview: 6:. Probiem 1: Diode Circuit Analysis: (20 pointsa tetal) Assuming that the diodes in the circuits are ideal, determine the diode states (ON or OFF) and find the value of voltages. (a) (b) 9V 9V 6V 20kQ D 1 D2 V We, 15,, gtflkfl (" . A ., :2 “mi? W.‘ v - Li '33 KM‘M m K n- ae; ire , {1% 3‘13 F I V *3 "“ S; V fitti- i‘ 3" "3” U“ 3 La? Wk it \r J a: gig; . fete f ‘3'???» Pmblem 2: CM'OS Inverter Analysis: (20 points, total) The NMOS has the parameters: V503 = + Vm : L0 v; K; 25 pA/VZ; W/L : 4/1; A z 0, y : 0.5 'st j Mp 1H and 2g)F : 0.6 V. And PMOS has the parameters: : VG VT‘PG '3 —1.{} V; K; : 10 “Ajvz; - m. W/L21/1;7\.E(‘),y:0.5 , and 2(1)]? :- T i |I|————J'_ _ MN 411 V00 3 5.0 V The CMOS gate is cafled pSeudo—NMOS. Find V1.1 and VL for this gate. m a? \z .3 1 “ M. r U sf"; I V _ k x L it“? {w W5 EV"? 9? 3 “2?; m \f M $2 at ‘ . v . . - ' {-1 i”? 1:" ix} L V§~i M V“ “r m‘ m W32: 3 Vim V“; €43 a?“ g Problem 3: CMOS Inverter Analysis: (39 points, total) "mm r ' v00: ~ w -— — - ~ +2. "1“pr _ _ pMOS 5” __V_1‘9.__ mmmmmm ,;_ _;9_£Y__ SE K’ 10 ilA/Vz Mp 5015 0 I MN 2015 “TV” ‘ MEY'w—m I D L L ‘ _ f w . V a m.” __‘L__ £33“ 2‘3”: 0.53.] This is a symmetrical CMOS Inverter {Ag 10 pointg] Calculate the noise margins NMH‘ : NML = NM for the inverter - a _ kg, ‘ ‘ t; M H .; "thmwib a M M a” £51.. ,_ i: 4t 3mg .. w ‘t a 6L? if I “um [13; 10 points] Caicqiate the steady~state DC drain currents when V; : VDD/Z Vs? : V3; « §.P<:‘i1»’xfi§';g.'f\'7§{?£§ m ’ ‘ ‘2.) t g; g a} f x I Wu ’3‘“ “3* t a! I --« v.1; it WEN km , “a? t w v *r M: £3... 7:, W "’5 7“ ‘. J g a £u_ w- t“ i‘ t “5 "t w.‘ g2; '2 "1 “‘ : r? u... I ‘5 -» [Cg 10 points} Calculate: the propagatiun delay time tpHL = 1‘9”; :1 t? if the inverter drives an equivalent lead capacitance 0f CL, r: LO [)3 www m Problem 4: Design a ifligital Subsystem: (30 points, total) (a) Design a depietien-load gate that implements the logic function Y=A[B+C(D+E)], based on the reference inverter design as shown. (b) with the parameters, ‘v'mg “—" 1.0 V; Kg 25 yANz; find the war; ratio of Ms if using the same NMOS for the driver and gives the V0:0.25 V, while : V913. and £1) “1 50 pAmp. Wu 's' VDD = +5 V A ML 112.15 V0 Vi '] MS 31%: mag _ fix: in. m "‘ v"; 3f“- ? k.“ -.i£.,, .3 i/ 5 ii ...
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Sample final - 6:. Probiem 1: Diode Circuit Analysis: (20...

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