DESIGN CONSIDERATIONS IN A BiCMOS DUAL-MODULUS PRESCALER

DESIGN CONSIDERATIONS IN A BiCMOS DUAL-MODULUS PRESCALER -...

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M03D-4 DESIGN CONSIDERATIONS IN A BiCMOS DUAL-MODULUS PRESCALER Fikret Diilger and Edgar Srinchez-Sinencio Texas A&M University Department of Electrical Engineering College Station, TX 77843-3 128 ABSTRACT Design considerations in a dual modulus divide by 32/33 prescaler with a 0.6pm BiCMOS process are presented. Care was taken to design the ECL-based circuits to operate with as low supply voltage and current consumption as possible. The phase noise contribution of the integrated bandgap bias network is demonstrated through simulations. The trade- off between the power consumption and the phase noise is pointed out and some guidelines are provided to improve the noise performance. Measurements confirm the hnctionality of the prescaler with a 2.5V supply drawing around 2.3mA at 2.35 GHz with an input sensitivity between -24dBm and l2dBm. The circuit operates with a supply voltage down to 2.1V but with limited input sensitivity. 1. INTRODUCTION Prescalers are among the key building blocks of GHz-range frequency synthesizers used in wireless communication sys- tems, [ 11, [2]. The quality of the prescaler is vital in set- ting the performance of the PLL-based frequency synthe- sizers used as Local Oscillators, especially from the power consumption point of view. There is a continuing research effort to improve the efficiency (i.e. higher operating fre- quency with lower power consumption) of the prescalers designed with the mainstream CMOS and BiCMOS tech- nologies, [3], [4]. However, the impact of the prescaler phase noise on the PLL output phase noise has not received much attention in the literature. The noise contributors in the prescalers are hardly investigated in the papers causing a lack of understanding to optimize the noise performance of the prescalers designed for wireless communication sys- tems. In this paper, after briefly emphasizing the impact of the prescaler noise on the phase noise performance of the PLL-based frequency synthesizers in Section 11, a dual- modulus prescaler design in a BiCMOS technology is pre- sented in Section 111. The trade-offs involved in the design The authors would like to acknowledge the support of Dr. Maher Abuzaid throughout the work and Texas Instruments for the fabrication of the chip and for providing the phase noise measurement system. Abdellatif Bellaouar Texas Instruments Incorporated Dallas, TX 75243 USA are mentioned with emphasis on the phase noise perfor- mance. The last two sections include the experimental re- sults and some conclusions, respectively. 2. PRESCALERS IN PLLs PLL-based frequency synthesizers are widely used in mod- ern communication systems, mostly in synthesizing well de- fined, stable local oscillator signals. Fig. 1. Phase-Locked Loop: (a) Basic block diagram, (b) Phase noise of a first-order loop with a low noise input One of the most challenging parts of especially high- frequency PLLs used in wireless communication systems is the prescaler due to the demanding specification of low power consumption and low phase noise at GHz frequen- cies. Block diagram of a basic PLL is shown in Fig.l(a),
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This note was uploaded on 12/14/2009 for the course ELECTRICAL ieee Radio taught by Professor Fikretdiilgerandedgarsrinchez-sinencio during the Spring '02 term at Texas A&M.

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DESIGN CONSIDERATIONS IN A BiCMOS DUAL-MODULUS PRESCALER -...

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