07_LC3_Architecture

07_LC3_Architecture - CMPE12 Cyrus Bazeghi 1 LC-3...

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Unformatted text preview: CMPE12 Cyrus Bazeghi 1 LC-3 Architecture (Ch4’ish material) CMPE12 Cyrus Bazeghi 2 CISC vs. RISC CISC : Complex Instruction Set Computer Lots of instructions of variable size, very memory optimal, typically less registers. RISC : Reduced Instruction Set Computer Less instructions, all of a fixed size, more registers, optimized for speed. Usually called a “Load/Store” architecture. CMPE12 Cyrus Bazeghi 3 What is “Modern” For embedded applications and for workstations there exist a wide variety of CISC and RISC and CISCy RISC and RISCy CISC. Most current PCs use the best of both worlds to achieve optimal performance. CMPE12 Cyrus Bazeghi 4 LC-3 Architecture o Very RISC, only 15 instructions o 16-bit data and address o 8 general purpose registers (GPR) o Program Counter (PC) o Instruction Register (IR) o Condition Code Register (CC) o Process Status Register (PSR) CMPE12 Cyrus Bazeghi 5 Instruction Fetch / Execute Cycle In addition to input & output a program also: • Evaluates arithmetic & logical functions to determine values to assign to variable. • Determines the order of execution of the statements in the program. In assembly this distinction is captured in the notion of Arithmetic, logical, and control instructions. CMPE12 Cyrus Bazeghi 6 Arithmetic and logical instructions evaluate variables and assign new values to variables. Control instructions test or compare values of a variable and makes decisions about what instruction is to be executed next. Program Counter (PC) Basically the address at which the current executing instruction exists. Instruction Fetch / Execute Cycle CMPE12 Cyrus Bazeghi 7 1. load rega, 10 2. load regb, 20 3. add regc, rega, regb 4. beq regc, regd, 8 5. store regd, rege 6. store regc, regd 7. load regb, 15 8. load rega, 30 PC Instruction Fetch / Execute Cycle Address *Note: This is just pseudo assembly code CMPE12 Cyrus Bazeghi 8 The CPU begins the execution of an instruction by supplying the value of the PC to the memory & initiating a read operation (fetch). The CPU “decodes” the instruction by identifying the opcode and the operands. PC increments automatically unless a control instruction is used. Instruction Fetch / Execute Cycle CMPE12 Cyrus Bazeghi 9 For example: PC ADD A, B, C o CPU fetches instruction o Decodes it and sees it is an “add” operation, needs to get values for the variables “B” & “C” o Gets the variable “B” from a register or memory o Does the same for variable “C” o Does the “add” operation and stores the result in location register for variable “A” Instruction Fetch / Execute Cycle CMPE12 Cyrus Bazeghi 10 Branch – like a goto instruction, next instruction to be fetched & executed is an instruction other than the next in memory....
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This note was uploaded on 12/14/2009 for the course CMPE 12/l taught by Professor Bazeghi during the Fall '09 term at UCSC.

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07_LC3_Architecture - CMPE12 Cyrus Bazeghi 1 LC-3...

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