08_LC3_ISA

08_LC3_ISA - LC-3 Instruction Set Architecture(Ch5 CMPE12 1...

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CMPE12 Cyrus Bazeghi 1 LC-3 Instruction Set Architecture (Ch5)
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CMPE12 Cyrus Bazeghi 2 Instruction Set Architecture ISA is all of the programmer-visible components and operations of the computer. memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes The ISA provides all the information needed for someone to write a program in machine language (or translate from a high-level language to machine language).
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CMPE12 Cyrus Bazeghi 3 Memory vs. Registers Memory address space: 2 16 locations (16-bit addresses) addressability: 16 bits Registers temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each is 16 bits wide how many bits to uniquely identify a register? other registers not directly addressable, but used/effected by instructions PC (program counter), condition codes LC-3 Overview
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CMPE12 Cyrus Bazeghi 4 Instruction Set Opcodes 15 opcodes Operate (Logical or Arithmetic) instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP some opcodes set/clear condition codes, based on result: N = negative (< 0), Z = zero, P = positive (> 0) Data Types 16- bit 2’s complement integer (we’ll get to that soon) Addressing Modes How is the location of an operand specified? non-memory addresses: immediate , register memory addresses: PC-relative , indirect , base+offset LC-3 Overview
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CMPE12 Cyrus Bazeghi 5 Operate Instructions Only three operations: ADD, AND, NOT Source and destination operands are registers These instructions do not reference memory. – ADD and AND can use “immediate” mode, where one operand is hard-wired into the instruction. Will show dataflow diagram with each instruction. illustrates when and where data moves to accomplish the desired operation LC-3 Overview
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CMPE12 Cyrus Bazeghi 6 NOT Note: Src and Dst could be the same register. Note: works only with registers. Instructions
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CMPE12 Cyrus Bazeghi 7 ADD/AND This zero means “register mode” Instructions
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CMPE12 Cyrus Bazeghi 8 ADD/AND Note: Immediate field is sign-extended . This one means “immediate mode” Instructions
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CMPE12 Cyrus Bazeghi 9 Using Operate Instructions With only ADD, AND, NOT… How do we subtract? How do we OR? How do we copy from one register to another? How do we initialize a register to zero?
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CMPE12 Cyrus Bazeghi 10 Data Movement Instructions Load -- read data from memory to register LD: PC-relative mode LDR: base+offset mode LDI: indirect mode Store -- write data from register to memory ST: PC-relative mode STR: base+offset mode STI: indirect mode Load effective address -- compute address, save in register LEA: immediate mode does not access memory
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This note was uploaded on 12/14/2009 for the course CMPE 12/l taught by Professor Bazeghi during the Fall '09 term at UCSC.

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08_LC3_ISA - LC-3 Instruction Set Architecture(Ch5 CMPE12 1...

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