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ECE 6130/4130: Advance VLSI Systems Fall 2009 Adders Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology

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Reading Materials Chapter 12 : Introduction to VLSI Circuits and Systems , Uyemura, Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
Half-adder : : . sum s a b carry c ab = = = =

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Half-adder logic diagram. : : . sum s a b carry c ab = = = =
Binary Adder: Full-adder ( ) 1 i i i i i i i i i i s a b c and c ab c a b + = = + The carryout bit can also be written as: ( ) 1 i i i i i i c ab c a b + = + +

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Static CMOS Full Adder ( ) ( ) 1 ( ) ( ) i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i s a b c ab a b c abc a bc a bc abc a c bc a b a b c abc a b c c abc + = = + = + + + = + + + + + = + + + ( ) 1 i i i i i i c ab c a b + = + + ( ) ( ) ( ) 1 . i i i i i i i i i i i i i i i i i c ab c a b a b c ab ac bc ab + = + + = + + = + +

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Static CMOS Full Adder 28 Transistors A B B A C i C i A X V DD V DD A B C i B A B V DD A B C i C i A B A C i B C o V DD S ( ) X i i i i i o ab c a b c = + + = ( ) i i i o i i i a b c c abc + + +
Mirror Adder: Carry-out circuit. ( ) 1 0 1 1 if: ( ) 0 0 ( ) '0' i i i i i i i i i c ab orc a b pull upshould beON a a and b bif oneis output isdeterimined byc + = => = + = => = =

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A Better Structure: The Mirror Adder V DD C i A B C i C i B A C i A B B A V DD S C o 1 1 1 ( ) : and ( ) in parallel = 1 (a)if 0 ( ) is '0' output is determined by i i i i i i i i i i i i i i i i i i i s a b c c abc pull down abc a b c c pull up network ouput if a b c or b if one or two c + + + = + + + + + = = =
The Mirror Adder V DD C i A B B A B A A B V DD C i A B C i C i B A C i A B B A V DD S C o 24 transistors

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Transmission-gate full-adder circuit. X Y Logic for X: b i =1 => T1 off =>X = !a i b i =0 => T1 on => X = a i T1 T2 i i i i i i X ab ab a b = + = Logic for Y: b i =1 => T2 on => Y = a i b i =0 => T2 off => Y = !a i i i i i i i Y ab ab a b Y X = + = => =

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