Adders - ECE 6130/4130: Advance VLSI Systems Fall 2009...

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ECE 6130/4130: Advance VLSI Systems Fall 2009 Adders Prof. Saibal Mukhopadhyay Georgia Institute of Technology
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Reading Materials Chapter 12 : Introduction to VLSI Circuits and Systems , Uyemura, • Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
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Half-adder : : . sum s a b carry c a b = = ⊕ = =
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Half-adder logic diagram. : : . sum s a b carry c a b = = ⊕ = =
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Binary Adder: Full-adder ( ) 1 i i i i i i i i i i s a b c and c a b c a b + = = + The carryout bit can also be written as: ( ) 1 i i i i i i c a b c a b + = + +
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Full-adder Logic Networks
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Static CMOS Full Adder ( ) ( ) 1 ( ) ( ) i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i s a b c a b a b c a b c a b c a b c a b c a c b c a b a b c a b c a b c c a b c + = = + = + + + = + + + + + = + + + ( ) 1 i i i i i i c a b c a b + = + + ( ) ( ) ( ) 1 . i i i i i i i i i i i i i i i i i c a b c a b a b c a b a c b c a b + = + + = + + = + +
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Static CMOS Full Adder 28 Transistors A B B A C i C i A X V DD V DD A B C i B A B V DD A B C i C i A B A C i B C o V DD S ( ) X i i i i i o a b c a b c = + + = ( ) i i i o i i i a b c c a b c + + +
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Mirror Adder: Carry-out circuit. ( ) 1 0 1 1 if: ( ) 0 0 ( ) '0' i i i i i i i i i c a b or c a b pull up should be ON a a and b b if one is output is deterimined by c + = => = + = => = =
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A Better Structure: The Mirror Adder V DD C i A B C i C i B A C i A B B A V DD S C o 1 1 1 ( ) : and ( ) in parallel = 1 (a)if 0 ( ) is '0' output is determined by i i i i i i i i i i i i i i i i i i i s a b c c a b c pull down a b c a b c c pull up network ouput if a b c or b if one or two c + + + = + + + + + = = =
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The Mirror Adder V DD C i A B B A B A A B V DD C i A B C i C i B A C i A B B A V DD S C o 24 transistors
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