CMOS_LOGIC_GATES - ECE 6130/4130: Advance VLSI Systems Fall...

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1 ECE ECE 6130/4130: 6130/4130: Advance VLSI Systems Advance VLSI Systems Fall 2009 Fall 2009 CMOS: Logic Gates CMOS: Logic Gates Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology
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2 Goals Goals ± Static CMOS logic gates ² simple logic gates - NAND and NOR ² Constructing complex gates ± Principles for better performance ± Logical effort ² Concept and applications
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3 Reading Materials Reading Materials ± Chapter 7 and 8 : Introduction to VLSI Circuits and Systems , Uyemura, ± Chapter 6: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic ± Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
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4 Static CMOS Static CMOS V DD F(In1,In2,…InN) In1 In2 InN In1 In2 InN PUN PDN PMOS only NMOS only PUN and PDN are dual logic networks
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5 NMOS Transistors NMOS Transistors in Series/Parallel Connection in Series/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high XY AB Y = X if A and B X Y A B Y = X if A OR B NMOS Transistors pass a “strong” 0 but a “weak” 1
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6 PMOS Transistors PMOS Transistors in Series/Parallel Connection in Series/Parallel Connection X Y AB Y = X if A AND B = A + B X Y A B Y = X if A OR B = AB PMOS Transistors pass a “strong” 1 but a “weak” 0 PMOS switch closes when switch control input is low
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7 Threshold Drops Threshold Drops V DD V DD 0 PDN 0 V DD C L C L PUN V DD 0 V DD -V Tn C L V DD V DD V DD |V Tp | C L S DS D V GS S S D D V GS
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8 Example Gate: NAND Example Gate: NAND
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9 Example Gate: NOR Example Gate: NOR
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10 Complex CMOS Gate Complex CMOS Gate OUT = D + A • (B + C) D A BC D A B C
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11 NAND Gates: DC Characteristics NAND Gates: DC Characteristics V A , V B V out both input switching only one input switching If both inputs switches from 0 to V DD , switching threshold is higher as both PMOS’s are initially ON
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12 Simplification of the series Simplification of the series - - connected connected FETs FETs . . Two devices with ox W C L βμ ⎛⎞ = ⎜⎟ ⎝⎠ Single device with (1) 22 ox W C L β ==
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13 Simplification of parallel Simplification of parallel - - connected connected FETs FETs . . Two devices with ox W C L βμ ⎛⎞ = ⎜⎟ ⎝⎠ Single device with (1) 2 2 ox W C L β μβ ==
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14 NAND Gates: Simultaneous Switching NAND Gates: Simultaneous Switching ( ) () 12 11 2 D Dt h p n p t h n M np VV V V ββ −+ = +
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15 Switching Characteristics: NAND2 Switching Characteristics: NAND2
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16 Switching Characteristics: NAND2 Switching Characteristics: NAND2 ( ) ( ) [] 2 0.69 and 0.69 2 n n out n X n FET L n X pLH P out pHL n out n X Fall time const R R C R C R C C R C t RC t =+ + = + + == + Low-to-high Transition High-to-Low Transition
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17 FET Sizing for NAND Gates FET Sizing for NAND Gates Neglect the internal node capacitances Consider worst-case delays Low-to-high -> when one input is switching High-to-low -> when both inputs are switching _2 _ _ 2 : 2 pLH P out pHL n out pLH pHL nN A N D nI N V pN A N D pI N V tR C C for t t ββ = = =
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This note was uploaded on 12/14/2009 for the course ECE 6130 taught by Professor Staff during the Fall '08 term at Georgia Institute of Technology.

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CMOS_LOGIC_GATES - ECE 6130/4130: Advance VLSI Systems Fall...

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