Dynamic_CMOS

# Dynamic_CMOS - ECE 6130/4130 Advance VLSI Systems Fall 2009...

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1 ECE ECE 6130/4130: 6130/4130: Advance VLSI Systems Advance VLSI Systems Fall Fall 2009 2009 Combinational Logic Styles: Part Combinational Logic Styles: Part - - II II Dynamic Logic Dynamic Logic Other Styles Other Styles Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology

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2 Reading Materials Reading Materials ± Chapter 9 : Introduction to VLSI Circuits and Systems , Uyemura, ± Chapter 6: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic ± Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
3 Dynamic CMOS Dynamic CMOS ± In static circuits at every point in time (except when switching) the output is connected to either GND or V DD via a low resistance path. ² fan-in of n requires 2 n ( n N-type + n P-type) devices ± Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes. ² requires on n + 2 ( n +1 N-type + 1 P-type) transistors

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4 Dynamic Gate Dynamic Gate In 1 In 2 PDN In 3 M e M p Clk Clk Out C L Out Clk Clk A B C M p M e Two phase operation Precharge (Clk = 0) Evaluate (Clk = 1) on off 1 off on ((AB)+C)
5 Conditions on Output Conditions on Output ± Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation. ± Inputs to the gate can make at most one transition during evaluation. ± Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

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6 Properties of Dynamic Gates Properties of Dynamic Gates ± Logic function is implemented by the PDN only ² number of transistors is N + 2 (versus 2N for static complementary CMOS) ± Full swing outputs (V OL = GND and V OH = V DD ) ± Non-ratioed - sizing of the devices does not affect the logic levels ±
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Dynamic_CMOS - ECE 6130/4130 Advance VLSI Systems Fall 2009...

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