Memory-I - ECE 6130/4130 Advance VLSI Systems Fall 2009...

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1 ECE 6130/4130: Advance VLSI Systems ECE 6130/4130: Advance VLSI Systems Fall 2009 Fall 2009 Memory Memory - - I: Static Random Access Memory I: Static Random Access Memory Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology
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2 Reading Materials Reading Materials ± Chapter 13 : Introduction to VLSI Circuits and Systems , Uyemura, ± Chapter 12: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic ± Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
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3 Array Array - - Structured Memory Architecture Structured Memory Architecture Row Decoder Bit line 2 L 2 K Word line A K A K 11 A L 21 A 0 M. 2 K A K Sense amplifiers / Drivers Column decoder Input-Output ( M bits) Storage cell Amplify swing to rail-to-rail amplitude Selects appropriate word - - - - M.2 k columns = 2 k words each with M bits Read/write ckts M bit data
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4 Array Array - - Structured Memory Architecture Structured Memory Architecture b 0 w 0 b 0 w 1 b 0 w 2 b 0 w 3 b 1 w 0 b 1 w 1 b 1 w 2 b 1 w 3 b 3 w 0 b 3 w 1 b 3 w 2 b 3 w 3 Col. MUX Col. MUX Col. MUX R/W ckts for each bit R/W ckts for each bit R/W ckts for each bit b 0 b 1 b 3 4 bit Word b 0 b 1 b 3 WL Col. Decoder (word selector) b m w n = bit ‘m’ of word ‘n’
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5 Array Array - - Structured Memory Architecture Structured Memory Architecture b 0 w 0 b 1 w 0 b 2 w 0 b 3 w 0 b 0 w 1 b 1 w 1 b 2 w 1 b 3 w 1 b 0 w 3 b 1 w 3 b 2 w 3 b 3 w 3 Column decoder (word selector) 4 bit Word w 0 w 1 w 3 WL b m w n = bit ‘m’ of word ‘n’ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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6 Hierarchical Memory Architecture Hierarchical Memory Architecture Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings 2. Block address activates only 1 block => power savings Global amplifier/driver Control circuitry Global data bus Block selector Block 0 Row address Column address Block address Block i Block P 21 I/O -
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7 Read Read - - Write Memories (RAM) Write Memories (RAM) ± STATIC (SRAM) ± DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
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8 6 6 - - transistor CMOS SRAM Cell transistor CMOS SRAM Cell WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q pull-up or load devices (M2, M4) pull-down devices (M1, M3) access or pass-gate devices (M5, M6) ± Data Holding ± Read ± Write
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9 Basic Principle of Data Storage in SRAM: Basic Principle of Data Storage in SRAM: Positive Feedback: Bi Positive Feedback: Bi - - Stability Stability V i1 V o2 V =V V o1 i2 V A C B V o2 V o2 V o1 V i2 V o1 A cross-coupled inverter provides a basic storage element
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10 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) V DD C bit V DD C bit PRE V DD cell cell WL 0 WL n PRE WL 0 BL BL BL BL V DD Δ BIT
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11 SRAM Cell: Read Operation SRAM Cell: Read Operation V DD C bit WL BL V DD M 5 M 6 M 4 M 1 M 2 M 3 BL Q Q = V DD ‘0’ ‘1’ V DD C bit
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12 CMOS SRAM Analysis (Read) CMOS SRAM Analysis (Read) WL BL V DD M 5 M 6 M 4 M 1 V DD V DD BL Q = 1 Q = 0 V DD C bit C bit M 1 in linear region
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Memory-I - ECE 6130/4130 Advance VLSI Systems Fall 2009...

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