Memory-II - ECE 6130/4130: Advance VLSI Systems Fall 2009...

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1 ECE 6130/4130: Advance VLSI Systems Fall 2009 Memory-II: Dynamic Random Access Memory Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology
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2 Reading Materials Chapter 13 : Introduction to VLSI Circuits and Systems , Uyemura, Chapter 12: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
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3 Read-Write Memories (RAM) STATIC (SRAM) DYNAMIC (DRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
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4 IT DRAM cell. Only one transistor: Very high density
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5 Hold operations in a DRAM cell. BL BL is precharged to V DD /2 Logic (1): Charge stored in the capacitor and V S = Q s C s Logic (0): No-charge stored in the capacitor and V S = 0
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6 Hold operations: Charge leakage Assuming a constant leakage current = I L Retention time or hold time = t h = (C S /I L ) V S ) V S The memory need to be refreshed periodically while storing the data
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7 1-Transistor DRAM Cell M 1 C S WL BL 1 Write ‘1’: V
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This note was uploaded on 12/14/2009 for the course ECE 6130 taught by Professor Staff during the Fall '08 term at Georgia Institute of Technology.

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Memory-II - ECE 6130/4130: Advance VLSI Systems Fall 2009...

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