Physical_Design-I

Physical_Design-I - ECE 6130/4130: Advance VLSI Systems...

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ECE 6130/4130: Advance VLSI Systems Fall 2009 Physical Design Prof. Saibal Mukhopadhyay Georgia Institute of Technology
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Reading Materials Lecture notes (posted in T-square, under “Resources/Lecture Slides”) More reading Chapter 5 : Introduction to VLSI Circuits and Systems , Uyemura, Chapter 2: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic
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CMOS Process
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Design Rules • Interface between designer and process engineer • Guidelines for constructing process masks • Unit dimension: Minimum line width – scalable design rules: lambda parameter – absolute dimensions (micron rules)
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Intra-Layer Design Rules Metal2 4 3 10 9 0 Well Active 3 3 Polysilicon 2 2 Different Potential Same Potential Metal1 3 3 2 Contact or Via Select 2 or 6 2 Hole
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Transistor Layout 1 2 5 3 Transistor
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Vias and Contacts 1 2 1 Via Metal to Poly Contact Metal to Active Contact 1 2 5 4 3 2 2
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Layer Purpose Active Active for NMOS and PMOS Poly Polysilicon line for NMOS/PMOS Nwell Nwell region for PMOS Pwell Pwell region for NMOS Nimplant Implant N+ to source/drain for NMOS Pimplant Implant P+ to source/drain for PMOS Contact Contacts - connect Metal1 to Poly or active vthg General use threshold implant vthh High threshold implant 45nm Process
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Physical_Design-I - ECE 6130/4130: Advance VLSI Systems...

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