Power_delivery

Power_delivery - ECE 6130/4130: Advance VLSI Systems Fall...

Info iconThis preview shows pages 1–8. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: ECE 6130/4130: Advance VLSI Systems Fall 2009 Power Delivery Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology Reading Materials • Chapter 14 : Introduction to VLSI Circuits and Systems , Uyemura, • Lecture notes (posted in T-square, under “Resources/Lecture Slides”) – Source: Digital Integrated Circuits by Rabaye et. al. • Chapter 9: Digital Integrated Circuits: Rabaye Power Distribution: Impact of Resistance • We have already learned how to drive RC interconnect • Impact of resistance is commonly seen in power supply distribution: – IR drop – Voltage variations • Power supply is distributed to minimize the IR drop and the change in current due to switching of gates RI Introduced Noise M 1 X I R R Δ V f pre D V V DD V DD- Δ V I A Quick Calculation • On current of MOS ~ 1mA/ μ m • Switching current drawn by an inverter of 1 μ m devices ~ 1mA • Sheet resistance ~ 0.05 Ω /sq • For a 2-cm long 1 μ m wide wire – R = 0.05*20,000 Ω = 1k Ω • Δ V = 1mA * 1k Ω = 1V Impact of Resistance • Lower effective voltage for logic – Lower performance • Delay increases at a lower supply voltage – Functionality issues • Different gates may provide different input/output voltage levels • Static power dissipation for static CMOS • Incorrect evaluation for dynamic logic • Current demand is time varying – Power supply voltage will also vary over time • A source of clock jitter Impact of Resistance • The voltage drop will also vary in space – The gates further from supply pin will have higher voltage drop – Gates closer to a large output driver (requires large current) can have a higher voltage drop Source: Cadence Impact of Resistance...
View Full Document

This note was uploaded on 12/14/2009 for the course ECE 6130 taught by Professor Staff during the Fall '08 term at Georgia Tech.

Page1 / 27

Power_delivery - ECE 6130/4130: Advance VLSI Systems Fall...

This preview shows document pages 1 - 8. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online