Power_dissipation_CMOS_Logic

# Power_dissipation_CMOS_Logic - ECE 6130/4130 Advance VLSI...

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1 ECE 6130/4130: Advance VLSI Systems ECE 6130/4130: Advance VLSI Systems Spring 2009 Spring 2009 Power Dissipation Power Dissipation Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology

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2 Reading Materials Reading Materials ± Chapter 7 : Introduction to VLSI Circuits and Systems , Uyemura, ± Chapter 6: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic ± Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
3 P avg = α 01 C L V dd 2 f clk Node Transition Activity and Power Node Transition Activity and Power Power dissipation depends on the switching activity α 0 1 switching activity 0 1 : probability of a 0 to 1 transition at output.

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4 Static CMOS Gates Static CMOS Gates ± 0 1 transistion => F was ‘0’ before the transition and becomes ‘1’ after the transition Logic gate I 0 I n F ( ) 01 0 1 0 0 1 p pp p α == If inputs are independent and uniformly distributed ( ) 00 0 1 2 2 22 2 N NN N N N N 0 = number of ‘0’ entries for F in the truth table N 1 = number of ‘1’ entries for F in the truth table
5 Example: 2 Example: 2 - - Input NOR Gate Input NOR Gate ± Assume ² inputs are uniformly distributed - i.e. 00, 01,10, 11 has equal probability of occurrences ² Only one input transition is possible in one clock cycle 0 1 1 0 1 0 0 0 1 1 0 0 F B A ( ) 2 00 01 4 2 3(4 3) 3 21 6 1 6 NN α == =

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6 Example: 2 Example: 2 - - Input NAND Gate Input NAND Gate ± Assume ²
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Power_dissipation_CMOS_Logic - ECE 6130/4130 Advance VLSI...

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