Sequential_Elements - ECE 6130/4130: Advance VLSI Systems...

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1 ECE 6130/4130: Advance VLSI Systems ECE 6130/4130: Advance VLSI Systems Fall 2009 Fall 2009 Sequential Elements Sequential Elements Prof. Saibal Mukhopadhyay School of Electrical & Computer Engineering Georgia Institute of Technology
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2 Reading Materials Reading Materials ± Chapter 11.6-11.8 : Introduction to VLSI Circuits and Systems , Uyemura, ± Chapter 7: Digital Integrated Circuits: A Design Perspectives, J. M. Rabaey, A. Chandrakasan, B. Nikolic ± Lecture notes (posted in T-square, under “Resources/Lecture Slides”)
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3 Sequential Logic Sequential Logic 2 storage mechanisms • positive feedback • charge-based COMBINATIONAL LOGIC Registers Outputs Next state CLK QD Current State Inputs
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4 Latches Latches Level Sensitive Level Sensitive In clk In Out Positive Latch CLK D G Q Out Out stable Out follows In In clk In Out Negative Latch CLK D G Q Out Out stable Out follows In Latch passes D input to Q at high or low level of the clock
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5 Registers of Flip Registers of Flip - - flops flops Edge Sensitive Edge Sensitive ± Register or Flip-flops D is passed to Q only at the clock edge D Clk Q Clk D Q Positive Edge -Triggered Negative Edge -Triggered D Clk Q Clk D Q
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6 Timing Definitions Timing Definitions t CLK t D t c-q t hold t setup t Q DATA STABLE DATA STABLE Register CLK DQ Setup time (t setup ): The time that the data input must be valid before CLK arrives Hold time (t hold ): The time the data input must remain valid after the CLK edge Clk-Q-delay (t c-q ): The propagation delay between CLK arrival and the data D being copied to Q
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7 Maximum Clock Frequency Maximum Clock Frequency FF’s LOGIC t p,comb φ Also: t cdreg + t cdlogic > t hold t cd : contamination delay = minimum delay t c-q + t p,comb + t setup = T
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8 Basic Principle of Sequential Element: Basic Principle of Sequential Element: Positive Feedback: Bi Positive Feedback: Bi - - Stability Stability V i1 V o2 V =V V o1 i2 V A C B V o2 V o2 V o1 V i2 V o1 A cross-coupled inverter provides a basic storage element
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9 Meta Meta - - Stability Stability Loop Gain should be larger than 1 in the transition region Loop Gain should be less than 1 in the stable region A C d B V i2 5V o1 V i1 o2 A C B V o2 A and B are stable points and C is the metastability point
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10 How to Change States?
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This note was uploaded on 12/14/2009 for the course ECE 6130 taught by Professor Staff during the Fall '08 term at Georgia Institute of Technology.

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Sequential_Elements - ECE 6130/4130: Advance VLSI Systems...

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