L3 - Karnaugh Maps & Combinational Logic Design

L3 - Karnaugh Maps & Combinational Logic Design -...

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1 Karnaugh Maps & Combinational Logic Design ECE 152A – Summer 2009 June 29, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment square6 Brown and Vranesic boxshadowdwn 4 Optimized Implementation of Logic Functions square6 4.1 Karnaugh Map square6 4.2 Strategy for Minimization boxshadowdwn 4.2.1 Terminology boxshadowdwn 4.2.2 Minimization Procedure square6 4.3 Minimization of Product-of-Sums Forms square6 4.4 Incompletely Specified Functions square6 4.8 Cubical Representation boxshadowdwn 4.8.1 Cubes and Hypercubes
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2 June 29, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment square6 Roth boxshadowdwn 1 Introduction Number Systems and Conversion square6 1.4 Representation of Negative Numbers square6 1.5 Binary Codes boxshadowdwn 4 Applications of Boolean Algebra Minterm and Maxterm Expansions square6 4.5 Incompletely Specified Functions June 29, 2009 ECE 152A - Digital Design Principles 4 Reading Assignment square6 Roth (cont) boxshadowdwn 5 Karnaugh Maps square6 5.1 Minimum Forms of Switching Functions square6 5.2 Two- and Three-Variable Karnaugh Maps square6 5.3 Four-Variable Karnaugh Maps square6 5.4 Determination of Minimum Expressions Using Essential Prime Implicants square6 5.5 Five-Variable Karnaugh Maps
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3 June 29, 2009 ECE 152A - Digital Design Principles 5 Canonical Forms square6 The canonical Sum-of-Products (SOP) and Product-of-Sums (POS) forms can be derived directly from the truth table but are (by definition) not simplified boxshadowdwn Canonical SOP and POS forms are “highest cost”, two-level realization of the logic function boxshadowdwn The goal of simplification and minimization is to derive a lower cost but equivalent logic function June 29, 2009 ECE 152A - Digital Design Principles 6 Simplification square6 Reduce cost of implementation by reducing the number of literals and product (or sum) terms boxshadowdwn Literals correspond to gate inputs and hence both wires and the size (fan-in) of the first level gates in a two-level implementation boxshadowdwn Product (Sum) terms correspond to the number of gates in the first level of a two-level implementation and the size (fan-in) of the second level gate
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4 June 29, 2009 ECE 152A - Digital Design Principles 7 Simplification square6 Algebraic Simplification boxshadowdwn Using theorems and properties of Boolean Algebra square6 Difficult with large number of variables and complex Boolean expressions square6 Most often incorporated into CAD Tools square6 Karnaugh Maps boxshadowdwn Graphical representation of logic function suitable for manual simplification and minimization June 29, 2009 ECE 152A - Digital Design Principles 8 Two-Variable Karnaugh Map square6 Location of minterms and maxterms on a two-variable map boxshadowdwn Index is the same, expansion is complementary 0 1 0 1 m 0 m 1 m 2 m 3 A B 0 1 0 1 M 0 M 1 M 2 M 3 A B
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5 June 29, 2009 ECE 152A - Digital Design Principles 9 Two-Variable Karnaugh Map square6 Simplification using xy + xy’ = x and x + x’y = x + y boxshadowdwn F= Σ m (0,2,3) 0 1 0 1 0 1 A B 1 1 F = A’B’ + AB’ + AB F = B’ (A’ + A) + AB F = B’ + AB F = (B’ + A) (B’ + B) F = B’ + A June 29, 2009
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