L4 - Propagation Delay, Circuit Timing &amp; Adder Design

# L4 - Propagation Delay, Circuit Timing & Adder Design

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1 Propagation Delay, Circuit ECE 152A – Summer 2009 July 6, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment s Brown and Vranesic b 2 Introduction to Logic Circuits s 2.9 Introduction to CAD Tools b 2.9.1 Design Entry b 2.9.2 Synthesis b 2.9.3 Functional Simulation b 2.9.4 Physical Design (2 nd edition) b 2.9.5 Timing Simulation (2 nd edition) b 2.9.4 Summary (1 st edition)

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2 July 6, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment s Brown and Vranesic (cont) b 3 Implementation Technology b 3.3.1 Speed of Logic Circuits s 3.5 Standard Chips b 3.5.1 7400-Series Standard Chips s 3.8 Practical Aspects b 3.8.3 Voltage Levels in Logic Gates b 3.8.4 Noise Margin b 3.8.5 Dynamic Operation of Logic Gates b 3.8.6 Power Dissipation in Logic Gates July 6, 2009 ECE 152A - Digital Design Principles 4 Reading Assignment s Brown and Vranesic (cont) b 5 Number Representation and Arithmetic Circuits s 5.1 Positional Number Representation b 5.1.1 Unsigned Numbers b 5.1.2 Conversion Between Decimal and Binary Systems b 5.1.3 Octal and Hexadecimal Representations s 5.2 Addition of Unsigned Numbers b 5.2.1 Decomposed Full-Adder b 5.2.2 Ripple-Carry Adder b 5.2.3 Design Example
3 July 6, 2009 ECE 152A - Digital Design Principles 5 Reading Assignment s Roth b 1 Introduction Number Systems and Conversion s 1.2 Number Systems and Conversion s 1.3 Binary Arithmetic b 8 Combinational Circuit Design and Simulation Using Gates s 8.3 Gate Delays and Timing Diagrams July 6, 2009 ECE 152A - Digital Design Principles 6 Properties of Digital Integrated Circuits s The Ideal Digital Circuit

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4 July 6, 2009 ECE 152A - Digital Design Principles 7 Digital IC Definitions s Amplitude and Voltage Transfer Characteristics July 6, 2009 ECE 152A - Digital Design Principles 8 Digital IC Definitions s Noise Margins b Sources of noise b Definition of noise margins
5 July 6, 2009 ECE 152A - Digital Design Principles 9 Propagation Delay s When gate inputs change, outputs don’t change instantaneously b This delay is known as “gate” or “propagation” delay PLH PHL t t = = 2 1 ε July 6, 2009 ECE 152A - Digital Design Principles 10 Propagation Delay b ε 1 is the propagation delay from input going high to output going low (inverting logic) s t PHL b ε 2 is the propagation delay from input going low to output going high (inverting logic) s t PLH b Terminology ( t PHL and t PLH ) always refers to the transition on the output (whether circuit is inverting or not)

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6 July 6, 2009 ECE 152A - Digital Design Principles 11 Propagation Delay s Multiple Gate Delays b Example assumes that t PLH and t PHL equal 20 ns for both AND and NOR gate s Not always the case for different transitions or different gate types July 6, 2009 ECE 152A - Digital Design Principles 12 Propagation Delay s Maximum propagation delay is the longest delay between an input changing value and the output changing value s The path that causes this delay is called the critical path
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## This note was uploaded on 12/18/2009 for the course ECE 152a taught by Professor Johnson during the Spring '07 term at UCSB.

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L4 - Propagation Delay, Circuit Timing & Adder Design

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