L6 - Latches, the D Flip-Flop and Counter Design

L6 - Latches, the D Flip-Flop and Counter Design - Latches...

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1 Latches, the D Flip-Flop & Counter Design ECE 152A – Summer 2009 July 20, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment s Brown and Vranesic b 7 Flip-Flops, Registers, Counters and a Simple Processor s 7.1 Basic Latch s 7.2 Gated SR Latch b 7.2.1 Gated SR Latch with NAND Gates s 7.3 Gated D Latch b 7.3.1 Effects of Propagation Delays
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2 July 20, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment s Brown and Vranesic (cont) b 7 Flip-Flops, Registers, Counters and a Simple Processor (cont) s 7.4 Master-Slave and Edge-Triggered D Flip-Flops b 7.4.1 Master-Slave D Flip-Flop b 7.4.2 Edge-Triggered D Flip-Flop b 7.4.3 D Flip-Flop with Clear and Preset b 7.4.4 Flip-Flop Timing Parameters (2 nd edition) July 20, 2009 ECE 152A - Digital Design Principles 4 Reading Assignment s Roth b 11 Latches and Flip-Flops s 11.1 Introduction s 11.2 Set-Reset Latch s 11.3 Gated D Latch s 11.4 Edge-Triggered D Flip-Flop
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3 July 20, 2009 ECE 152A - Digital Design Principles 5 Reading Assignment s Roth (cont) b 12 Registers and Counters s 12.1 Registers and Register Transfers s 12.2 Shift Registers s 12.3 Design of Binary Counters s 12.4 Counters for Other Sequences July 20, 2009 ECE 152A - Digital Design Principles 6 Combinational vs. Sequential Logic s Combinational logic b Function of present inputs only s Output is known if inputs (some or all) are known s Sequential logic b Function of past and present inputs s Memory or “state” s Output known if present input and present state are known b Initial conditions often unknown (or undefined)
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4 July 20, 2009 ECE 152A - Digital Design Principles 7 Gate Delays s Recall from earlier lecture b When gate inputs change, outputs don’t change instantaneously July 20, 2009 ECE 152A - Digital Design Principles 8 Feedback s Outputs connected to inputs b Single inverter feedback s If propagation delay is long enough, output will oscillate
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5 July 20, 2009 ECE 152A - Digital Design Principles 9 Feedback b If the propagation delay is not long enough, the output will settle somewhere in the middle s V in = V out July 20, 2009 ECE 152A - Digital Design Principles 10 Feedback b Ring Oscillator s Any odd number of inverters will oscillate b ½ period = total prop delay of chain
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This note was uploaded on 12/18/2009 for the course ECE 152a taught by Professor Johnson during the Spring '07 term at UCSB.

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L6 - Latches, the D Flip-Flop and Counter Design - Latches...

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