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L8 - Sequential Design with Verilog

# L8 - Sequential Design with Verilog - Sequential Circuit...

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1 Sequential Circuit Design with Verilog ECE 152A – Summer 2009 July 29, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment square6 Brown and Vranesic boxshadowdwn 6 Combinational – Circuit Building Blocks square6 6.6 Verilog for Combinational Circuits boxshadowdwn 6.6.1 The Conditional Operator boxshadowdwn 6.6.2 The If-Else Statement boxshadowdwn 6.6.3 The Case Statement

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2 July 29, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment square6 Brown and Vranesic (cont) boxshadowdwn 7 Flip-Flops, Registers, Counters, and a Simple Processor square6 7.12 Using Storage Elements with CAD Tools boxshadowdwn 7.12.2 Using Verilog Constructs for Storage Elements boxshadowdwn 7.12.3 Blocking and Non-Blocking Assignments boxshadowdwn 7.12.4 Non-Blocking Assignments for Combinational Circuits boxshadowdwn 7.12.5 Flip-Flops with Clear Capability square6 7.13 Using Registers and Counters with CAD Tools boxshadowdwn 7.13.3 Using Verilog Constructs for Registers and Counters July 29, 2009 ECE 152A - Digital Design Principles 4 The Gated D Latch square6 Transparent on high phase of clock module D_latch(D, Clk, Q); input D, Clk; output Q; reg Q; always @(D or Clk) if (Clk) Q = D; endmodule
3 July 29, 2009 ECE 152A - Digital Design Principles 5 The Gated D Latch square6 The “if” construct boxshadowdwn When D or CLK change value: square6 if CLK = 1, set Q = D boxshadowdwn Since there is no else, assignment occurs only when CLK = 1 square6 Q follows D when CLK = 1 square6 Q remains latched on CLK = 0 boxshadowdwn “Always” construct triggered by change in value of D or CLK square6 Either change can cause the output to change July 29, 2009 ECE 152A - Digital Design Principles 6 The Gated D Latch square6 The “always” construct boxshadowdwn Responds to changes in the signals on the sensitivity list square6 always @ (D or Clk) boxshadowdwn Example above is “level sensitive” square6 When D or Clk changes value boxshadowdwn Make edge triggered by using Verilog keywords posedge and negedge square6 i.e., always @ (posedge Clk)

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4 July 29, 2009 ECE 152A - Digital Design Principles 7 The Edge Triggered D Flip-Flop square6 Positive edge triggered module flipflop(D, Clock, Q); input D, Clock; output Q; reg Q; always @(posedge Clock) Q = D; // Q + = D, characteristic function endmodule July 29, 2009 ECE 152A - Digital Design Principles 8
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