L8 - Sequential Design with Verilog

L8 - Sequential Design with Verilog - Sequential Circuit...

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1 Sequential Circuit Design with Verilog ECE 152A – Summer 2009 July 29, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment s Brown and Vranesic b 6 Combinational – Circuit Building Blocks s 6.6 Verilog for Combinational Circuits b 6.6.1 The Conditional Operator b 6.6.2 The If-Else Statement b 6.6.3 The Case Statement
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2 July 29, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment s Brown and Vranesic (cont) b 7 Flip-Flops, Registers, Counters, and a Simple Processor s 7.12 Using Storage Elements with CAD Tools b 7.12.2 Using Verilog Constructs for Storage Elements b 7.12.3 Blocking and Non-Blocking Assignments b 7.12.4 Non-Blocking Assignments for Combinational Circuits b 7.12.5 Flip-Flops with Clear Capability s 7.13 Using Registers and Counters with CAD Tools b 7.13.3 Using Verilog Constructs for Registers and Counters July 29, 2009 ECE 152A - Digital Design Principles 4 The Gated D Latch s Transparent on high phase of clock module D_latch(D, Clk, Q); input D, Clk; output Q; reg Q; always @(D or Clk) if (Clk) Q = D; endmodule
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3 July 29, 2009 ECE 152A - Digital Design Principles 5 The Gated D Latch s The “if” construct b When D or CLK change value: s if CLK = 1, set Q = D b Since there is no else, assignment occurs only when CLK = 1 s Q follows D when CLK = 1 s Q remains latched on CLK = 0 b “Always” construct triggered by change in value of D or CLK s Either change can cause the output to change July 29, 2009 ECE 152A - Digital Design Principles 6 The Gated D Latch s The “always” construct b Responds to changes in the signals on the sensitivity list s always @ (D or Clk) b Example above is “level sensitive” s When D or Clk changes value b Make edge triggered by using Verilog keywords posedge and negedge s i.e., always @ (posedge Clk)
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July 29, 2009 ECE 152A - Digital Design Principles 7 The Edge Triggered D Flip-Flop s Positive edge triggered module flipflop(D, Clock, Q); input D, Clock; output Q; reg Q; always @(posedge Clock) Q = D; // Q + = D, characteristic function endmodule July 29, 2009 ECE 152A - Digital Design Principles 8 The Edge Triggered D Flip-Flop s D is not included on sensitivity list since it cannot cause output (Q) to change b No transparent phase with edge triggered flip-
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L8 - Sequential Design with Verilog - Sequential Circuit...

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