{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

L9 - Mealy and Moore Machines

L9 - Mealy and Moore Machines - Mealy and Moore Machines...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Mealy and Moore Machines ECE 152A – Summer 2009 August 3, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment square6 Brown and Vranesic boxshadowdwn 8 Synchronous Sequential Circuits square6 8.3 Mealy State Model
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 August 3, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment square6 Roth boxshadowdwn 13 Analysis of Clocked Sequential Circuits square6 13.1 A Sequential Parity Checker square6 13.2 Analysis by Signal Tracing and Timing Charts square6 13.3 State Tables and Graphs square6 13.4 General Models for Sequential Circuits August 3, 2009 ECE 152A - Digital Design Principles 4 Finite State Machines square6 Thus far, sequential circuit (counter and register) outputs limited to state variables square6 In general, sequential circuits (or Finite State Machines, FSM’s) have outputs in addition to the state variables boxshadowdwn For example, vending machine controllers generate output signals to dispense product, provide change, illuminate displays, etc.
Background image of page 2
3 August 3, 2009 ECE 152A - Digital Design Principles 5 Finite State Machines square6 Two types (or models) of sequential circuits (or finite state machines) boxshadowdwn Mealy machine square6 Output is function of present state and present input boxshadowdwn Moore machine square6 Output is function of present state only square6 Analysis first, then proceed to the design of general finite state machines August 3, 2009 ECE 152A - Digital Design Principles 6 Analysis by Signal Tracing and Timing Diagrams square6 Timing Analysis boxshadowdwn Determine flip-flop input equations boxshadowdwn Determine output equations square6 Mealy or Moore model boxshadowdwn Generate timing diagram illustrating circuit’s response to a particular input sequence square6 Outputs as well as to state
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
4 August 3, 2009 ECE 152A - Digital Design Principles 7 Moore Network Example square6 Implemented with falling edge triggered (by way of external inverter) JK flip-flops square6 Schematic (following slide) boxshadowdwn J A = x K A = xB’ boxshadowdwn J B = x K B = x XOR A’ = xA + x’A’ boxshadowdwn z = B (function of present state only) August 3, 2009 ECE 152A - Digital Design Principles 8 Moore Network Example square6 Schematic
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}