L9 - Mealy and Moore Machines

L9 - Mealy and Moore Machines - Mealy and Moore Machines...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Mealy and Moore Machines ECE 152A – Summer 2009 August 3, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment s Brown and Vranesic b 8 Synchronous Sequential Circuits s 8.3 Mealy State Model
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
2 August 3, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment s Roth b 13 Analysis of Clocked Sequential Circuits s 13.1 A Sequential Parity Checker s 13.2 Analysis by Signal Tracing and Timing Charts s 13.3 State Tables and Graphs s 13.4 General Models for Sequential Circuits August 3, 2009 ECE 152A - Digital Design Principles 4 Finite State Machines s Thus far, sequential circuit (counter and register) outputs limited to state variables s In general, sequential circuits (or Finite State Machines, FSM’s) have outputs in addition to the state variables b For example, vending machine controllers generate output signals to dispense product, provide change, illuminate displays, etc.
Background image of page 2
3 August 3, 2009 ECE 152A - Digital Design Principles 5 Finite State Machines s Two types (or models) of sequential circuits (or finite state machines) b Mealy machine s Output is function of present state and present input b Moore machine s Output is function of present state only s Analysis first, then proceed to the design of general finite state machines August 3, 2009 ECE 152A - Digital Design Principles 6 Analysis by Signal Tracing and Timing Diagrams s Timing Analysis b Determine flip-flop input equations b Determine output equations s Mealy or Moore model b Generate timing diagram illustrating circuit’s response to a particular input sequence s Outputs as well as to state
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
4 August 3, 2009 ECE 152A - Digital Design Principles 7 Moore Network Example s Implemented with falling edge triggered (by way of external inverter) JK flip-flops s Schematic (following slide) b J A = x K A = xB’ b J B = x K B = x XOR A’ = xA + x’A’ b z = B (function of present state only) August 3, 2009 ECE 152A - Digital Design Principles 8 Moore Network Example s Schematic
Background image of page 4
Image of page 5
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 12/18/2009 for the course ECE 152a taught by Professor Johnson during the Spring '07 term at UCSB.

Page1 / 14

L9 - Mealy and Moore Machines - Mealy and Moore Machines...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online