homework 3

# homework 3 - ECE 152A Summer 2009 University of California...

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ECE 152A – Summer 2009 7/20/2009 Homework #3 – Page 1 of 5 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #3 Problem #1. Construct a timing diagram for the circuit shown below. Make the following assumptions: OUT is initially 1; the EN signal is low for the first 10 ns then goes high forever; all gate delays are 10 ns. Show the EN, A, B and OUT signals as a function of time for 70 ns. Problem #2. For the latch shown below,

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7/20/2009 Homework #3 – Page 2 of 5 Determine the following: 1. Characteristic Table 2. Characteristic Equation 3. State Diagram 4. State Table Problem #3. Complete the timing diagram (on the following page) for the logic diagram shown below. Assume the propagation delay for gates 1 and 2 is 10 ns and the propagation delay for gates 3 and 4 is 5 ns (both low to high and high to low transitions, t PLH and t PHL ). Include arrows on your timing diagram indicating the sequence and
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homework 3 - ECE 152A Summer 2009 University of California...

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