homework 3 solution

homework 3 solution - ECE 152A Summer 2009 7/27/2009...

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ECE 152A – Summer 2009 7/27/2009 Homework #3 Solution – Page 1 of 13 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #3 – Solution Problem #1. Construct a timing diagram for the circuit shown below. Make the following assumptions: OUT is initially 1; the EN signal is low for the first 10 ns then goes high forever; all gate delays are 10 ns. Show the EN, A, B and OUT signals as a function of time for 70 ns.
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ECE 152A – Summer 2009 7/27/2009 Homework #3 Solution – Page 2 of 13 Problem #2. For the latch shown below,
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ECE 152A – Summer 2009 7/27/2009 Homework #3 Solution – Page 3 of 13 Determine the following: 1. Characteristic Table 2. Characteristic Equation
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ECE 152A – Summer 2009 7/27/2009 Homework #3 Solution – Page 4 of 13 3. State Diagram 4. State Table
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ECE 152A – Summer 2009 7/27/2009 Homework #3 Solution – Page 5 of 13 Problem #3. Complete the timing diagram (on the following page) for the logic diagram shown
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homework 3 solution - ECE 152A Summer 2009 7/27/2009...

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