homework 4

# homework 4 - ECE 152A Summer 2009 University of California...

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ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 1 of 9 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #4 Problem #1. A JN flip flop is constructed by (internally) complementing the K input to an otherwise normal JK flip flop. For the JN flip flop, derive the following: 1. The characteristic table 2. The characteristic equation 3. The state table 4. The state diagram 5. The excitation table Problem #2. Design a 2-bit, binary up/down counter. The counter has 2 inputs, up_down and enable. The truth table below defines the operation of the counter: enable up_down | operation 0 0 | hold count 0 1 | hold count 1 0 | decrement count 1 1 | increment count Use positive edge triggered JK flip flops. In your answer, include (1) a state diagram, (2) a state table, (3) a next state map and (4) all Kmaps used in determining flip flop inputs Problem #3. Design a three bit counter with a single input called mode . The counter counts in binary if the mode bit is zero, and counts in gray code if the mode bit is one (recall the three bit gray code is 000, 001, 011, 010, 110, 111, 101, 100). The mode bit can change at any time during the count sequence and your counter should begin counting in the new mode on the next clock input.

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ECE 152A – Summer 2009 7/27/2009 Homework #4 – Page 2 of 9 Design the counter using JK flip flops. You don’t have to draw the logic diagram, specifying the J and K inputs to each flip flop is sufficient. Use A, B and C as the state variable names. Include (1) a state table, (2) next state maps and (3) K-maps for all flip flop inputs. Problem #4. Consider the flip flop illustrated below: 1. Would this flip flop function as a positive (rising) or negative (falling) edge triggered flip flop (and why)? 2. Construct the characteristic table for this flip flop.
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homework 4 - ECE 152A Summer 2009 University of California...

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