su07 midterm 2

# su07 midterm 2 - ECE 152A Summer 2007 University of...

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ECE 152A – Summer 2007 8/8/2007 Midterm Exam #2 – Page 1 of 16 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Midterm Exam #2 August 8, 2007 Name _____________________________________ Perm # ____________________________________ Lab Section _______________________________ Problem #1 (25 points) ____________ Problem #2 (25 points) ____________ Problem #3 (25 points) ____________ Problem #4 (25 points) ____________ Total (100 points) ____________ This is a 75 minute exam; closed book, closed notes, no calculators. Answer all questions on the exam.

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ECE 152A – Summer 2007 8/8/2007 Midterm Exam #2 – Page 2 of 16 Problem #1. Complete the timing diagram (on the following page) for the circuit shown below. Assume all gate delays are equal and all are much shorter than the clock period. You can also assume that both setup and hold times are satisfied. I’m more interested in the order of transitions (indicated by arrows, as shown on the timing diagram), than the detailed timing numbers.
ECE 152A – Summer 2007 8/8/2007 Midterm Exam #2 – Page 3 of 16

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ECE 152A – Summer 2007 8/8/2007 Midterm Exam #2 – Page 4 of 16 Problem #2. In this problem, you are to design a 3-bit counter which can function as either a modulo 5 counter (0,1,2,3,4,0…) or a Fibonacci Sequence counter (0,1,1,2,3,5,0...), based on a single input B. When B is high the counter counts in binary (mod 5); when B is low the counter sequences through the first 6 Fibonacci numbers.
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