L10 - Finite State Recognizers

L10 - Finite State Recognizers - Finite State Recognizers...

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1 Finite State Recognizers and Sequence Detectors ECE 152A – Summer 2009 August 10, 2009 ECE 152A - Digital Design Principles 2 Reading Assignment s Brown and Vranesic b 8 Synchronous Sequential Circuits s 8.4 Design of Finite State Machines Using CAD Tools b 8.4.1 Verilog Code for Moore-Type FSMs b 8.4.2 Synthesis of Verilog Code b 8.4.3 Simulating and Testing the Circuit b 8.4.4 Alternative Styles of Verilog Code b 8.4.5 Summary of Design Steps When Using CAD Tools b 8.4.6 Specifying the State Assignment in Verilog Code b 8.4.7 Specification of Mealy FSMs Using Verilog
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2 August 10, 2009 ECE 152A - Digital Design Principles 3 Reading Assignment s Roth b 14 Derivation of State Graphs and Tables s 14.1 Design of a Sequence Detector s 14.2 More Complex Design Problems s 14.2 Guidelines for Construction of State Graphs August 10, 2009 ECE 152A - Digital Design Principles 4 Mealy and Moore Machines s Mealy Machine b Output is a function of present state and present input s Outputs valid on clock edge (transition) b Simpler (possibly) b Faster (possibly) b Outputs “glitch” b Used for synchronous (clocked) designs
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3 August 10, 2009 ECE 152A - Digital Design Principles 5 Mealy and Moore Machines s Moore Machine b Output is a function of present state only s Outputs valid after state transition b More “stable” than Mealy machine s Outputs do not glitch b Asynchronous (no clock) or synchronous designs August 10, 2009 ECE 152A - Digital Design Principles 6 Deterministic Recognizers s State Diagram b Also referred to as Deterministic Transition Graph b Next state transition is determined uniquely by present state and present input s Deterministic Recognizer b Classifies input strings into two classes: s Those it accepts s Those it rejects
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4 August 10, 2009 ECE 152A - Digital Design Principles 7 Deterministic Recognizers s Sequential Lock Analogy b Accepted string corresponds to of the combination of the lock s Accepted string opens the lock s Rejected string leaves the lock closed s Provides a basis for general purpose, finite state machine (FSM) design b Controllers, peripheral interfaces, etc. August 10, 2009
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This note was uploaded on 12/18/2009 for the course ECE 152a taught by Professor Johnson during the Spring '07 term at UCSB.

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L10 - Finite State Recognizers - Finite State Recognizers...

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