homework 5

homework 5 - ECE 152A Summer 2009 8/3/2009 University of...

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ECE 152A – Summer 2009 8/3/2009 Homework #5 – Page 1 of 6 University of California, Santa Barbara Department of Electrical and Computer Engineering ECE 152A – Digital Design Principles Homework #5 Problem #1. For the logic diagram below, complete the timing diagram. You can assume the gate delays are much shorter than the clock period. Is this a Mealy machine or a Moore machine and why?
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ECE 152A – Summer 2009 8/3/2009 Homework #5 – Page 2 of 6
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ECE 152A – Summer 2009 8/3/2009 Homework #5 – Page 3 of 6 Problem #2. For the network shown below: 1. Construct a timing diagram for the input sequence: X = 0 1 0 1 0 1 1 1 0 Assume that: 1) X, A and B are all initially equal to 0 2) All transitions of the input X occur on the rising edge of the clock 3) gate delays are much shorter than the clock period. Include all inputs (CLK, X) state variables (A, B) and outputs (Z) in your timing diagram. 2. Construct next state maps for the network.
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This note was uploaded on 12/18/2009 for the course ECE 152a taught by Professor Johnson during the Spring '07 term at UCSB.

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homework 5 - ECE 152A Summer 2009 8/3/2009 University of...

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