HW3.sols.09

# HW3.sols.09 - Computer Architecture Homework 3 Due Monday...

This preview shows pages 1–3. Sign up to view the full content.

Computer Architecture Homework 3 Due: Monday, October 12, 2009 SOLUTIONS Consider the following code fragment: loop: LW R1, 0(R2) ADDI R1, R1, #1 LW R3, 0(R5) SW R1, 0(R2) ADD R2, R2, R3 ADDI R4, R4, #-4 BNEZ R4, loop Before the loop begins execution, the value in R4 is 64 (decimal). 1. This loop executes 16 times. The value in R4 = 64 on iteration 1 when the BNEZ is executed and is decremented by 4 each time through. The last execution (when the branch is not taken) is the 16 th execution of the loop. In each iteration of the loop, there are: 2 load instructions 1 store instruction 3 ALU instructions 1 conditional branch instruction The resulting instruction mix is: Instruction Type Frequency load 28.57% store 14.29% ALU 42.85% cond branch 14.29% The code to be traced for problems 2 and 3 is: I1 LW R1, 0(R2) I2 ADDI R1, R1, #1 I3 LW R3, 0(R5) I4 SW R1, 0(R2) I5 ADD R2, R2, R3 I6 ADDI R4, R4, #-4 I7 BNEZ R4, loop I8 LW R1, 0(R2)

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Answer to Problem 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 12/20/2009 for the course ECE 466 taught by Professor Staff during the Fall '09 term at Clarkson University .

### Page1 / 3

HW3.sols.09 - Computer Architecture Homework 3 Due Monday...

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online