HW3 - Computer Architecture Homework 3 Due: Monday, October...

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Computer Architecture Homework 3 Due: Monday, October 12, 2009 Consider the following code fragment: loop: LW R1, 0(R2) ADDI R1, R1, #1 LW R3, 0(R5) SW R1, 0(R2) ADD R2, R2, R3 ADDI R4, R4, #-4 BNEZ R4, loop Before the loop begins execution, the value in R4 is 64 (decimal). 1. How many iterations does this loop execute? If this loop is the entire program, what is the instruction mix? (That is, what percentage of the instructions are ALU instructions, what percentage are loads, what percentage are stores, and what percentage are conditional branches?) 2. Assume the classic 5 stage MIPS pipeline as discussed in class without any forwarding. Thus an instruction that uses register R as an operand cannot perform its decode (D) cycle earlier than the same cycle in which the instruction producing R’s value does its write (W). Also assume that branches are resolved in MEM and that register writes occur in the 1 st half of the clock cycle and register reads occur on the 2 nd half. Make a timing chart similar to the one shown below to show the timing of
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This note was uploaded on 12/20/2009 for the course ECE 466 taught by Professor Staff during the Fall '09 term at Clarkson University .

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HW3 - Computer Architecture Homework 3 Due: Monday, October...

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