Tomasulo - --------------------|--------------------cycle

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a. Using the MIPS code for DAXPY above, assume Tomasulo’s algorithm with speculation as shown in Figure 3.29. Assume the latencies shown in Figure 3.63. Assume that there are separate integer function units for effective address calculation, for ALU operations, and for branch condition evaluation. Create a table as in Figure 3.34 for the first three iterations of this loop. a. Assume dual issue. b. Assume you have 2 CDB’s; thus you can commit at most 2 instructions per cycle. c. You have as many ROB slots as you need. Solution (This is for pipelined FP FU) |------------------- cycle 1
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Unformatted text preview: --------------------|--------------------cycle 2--------------------|-------------------cycle 3--------------------| I EX WB (CDB) C I EX WB (CDB) C foo L.D F2, 0(R1) 1 2 3 4 6 7 8 28 MUL.D F4, F2, F0 1 4-18 19 20 6 9-23 24 28 L.D F6, 0(R2) 2 3 4 20 ADD F6, F4, F6 2 20-23 24 25 S.D F6, 0(R2) 3 25-25 DADDUI R1, R1, #8 3 4 5 26 DADDUI R2, R2, #8 4 5 6 26 DSGTUI R3, R1, #800 4 6 7 27 BEQZ R3,foo 5 7-27 Occupied slots in the reservation stations (bolded numbers are cycle numbers) 1 2 3 4 5 6 7 8 9 10 11 1 1 st LD X X 2 nd LD X SD 1 st DADDUI 2 nd DADDUI DSGTUI...
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