A-03 - iteration in the same manner) (This is with a...

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a. Use the MIPS code for DAXPY above and a fully pipelined FPU with the latencies of Figure 3.63. Assume a two-issue Tomasulo’s algorithm for the hardware with one integer unit taking one execution cycle (a latency of 1 cycle to use) for all integer operations. Show the number of stall cycles for each instruction and what clock cycle each instruction begins execution (i.e., enters its first EX cycle) for three iterations of the loop. Show your answer in the form of a table like that in Figure 3.25. Hint : pay attention to when the reservation stations are filled. a. Assume no branch prediction b. Assume 2 CDB’s; thus 2 WB can occur per stage Solution Here is the first iteration, and beginning of second iteration (fill out the third
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Unformatted text preview: iteration in the same manner) (This is with a pipelined FP FU) |-------------------cycle 1--------------------|-------------------cycle 2--------------------|-------------------cycle 3--------------------| I EX WB (CDB) I EX WB (CDB) foo: L.D F2, 0(R1) 1 2 3 7 8 9 MUL.D F4, F2, F0 1 4-18 19 7 10-24 25 L.D F6, 0(R2) 2 3 4 ADD F6, F4, F6 2 20-23 24 S.D F6, 0(R2) 3 25-DADDUI R1, R1, #8 3 4 5 DADDUI R2, R2, #8 4 5 6 DSGTUI R3, R1, #800 4 6 7 BEQZ R3,foo 5 7-Make sure to consider how many functional units are occupied. For instance, here is a table showing the instructions occupying the integer reservation stations for the first few cycles 1 2 3 4 5 6 7 8 9 10 19 1 st LD X X 2 nd LD X SD 1 st DADDUI 2 nd DADDUI DSGTUI...
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