A-02 - cycle 2--------------------|-------------------cycle

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a. For this problem use the single-issue Tomasulo MIPS pipeline of Figure 3.2 with the pipeline latencies from table above. Show the number of stall cycles for each instruction and what clock cycles each instruction begins execution (i.e., enters its first EX cycle) for three iterations of the loop. How many clock cycles does each loop iteration take? Report your answer in the form of a table like that in Figure 3.25. Assume 1 CDB, only 1 WB per cycle at a time Solution Here is the first iteration, and beginning of second iteration (fill out the third iteration in the same manner) (This is with a pipelined FP FU) |------------------- cycle 1 --------------------|-------------------
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Unformatted text preview: cycle 2--------------------|-------------------cycle 3--------------------| I EX WB (CDB) I EX WB (CDB) foo L.D F2, 0(R1) 1 2 3 10 11 12 MUL.D F4, F2, F0 2 4-18 19 11 13-27 28 L.D F6, 0(R2) 3 4 5 ADD F6, F4, F6 4 20-23 24 S.D F6, 0(R2) 5 25-DADDUI R1, R1, #8 6 7 8 DADDUI R2, R2, #8 7 8 9 DSGTUI R3, R1, #800 8 9 10 BEQZ R3,foo 9 10-Make sure to consider how many functional units are occupied. For instance, here is a table showing the instructions occupying the integer reservation stations for the first few cycles 1 2 3 4 5 6 7 8 9 10 11 …. N 1 st LD X X 2 nd LD S.D 1 st DADDUI 2 nd DADDUI DSGTUI...
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This note was uploaded on 12/20/2009 for the course ECE 466 taught by Professor Staff during the Fall '09 term at Clarkson University .

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