Unformatted text preview: for loads and stores. Thus the pipeline is IF/ID/IS/EX/WB, so LD/ST can execute in the same cycle as the address calculation. • Loads take 1 cycle (always a cache hit). • The issue (IS) and write result (WB) stages each take 1 clock cycle. • There are 5 load buffer slots and 5 store buffer slots. • Assume that the BEQZ instruction takes 0 clock cycles, this means that it means that there BEQZ must wait until all data dependences are resolved, after which there is no latency in the EX, also there is no latency between EX and the issue cycle of the next instruction • When doing LD/ST address calculation LD/ST done in same cycle (MEM/EX cone at the same time so no need for MEM column on page 222) • Assume FU is free starting at WB • Assume the reservation station becomes free at the WB stage • Assume BEQZ does not take up a slot in the reservation station...
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- Fall '09
- Computer Architecture, Clock signal, Instruction processing, WB stage Assume, address calculation, common vector loop