Cache performance

Cache performance - Leveltwoinstrcachehitlatency=6cycles

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Level two instr cache hit latency = 6 cycles  TLB data cache (64:4096:4:l) size = 1M TLB instr cache (32:4096:4:l) size = 512K Based on the above configuration, I then executed sim-outorder leaving unspecified  parameters at their default values. The code for the execution is as follows: ./sim-outorder –tlb:dtlb dtlb:64:4096:4:l –tlb:itlb itlb:32:4096:4:l –cache:dl1 dl1:128:32:4:l  –cache:il1   il1:512:16:4:l   –cache:dl2:   dl2:1024:512:2:l   –cache:il2   dl2   –redir:sim  results/anagram7.out   –redir:prog   results/anagram8.out   tests-pisa/bin.little/anagram  tests-pisa/inputs/words <tests-pisa/inputs/myinput.txt SIMULATION RESULT: The simulation output file “anagram7.out” produced a number of statistics; a summary of  the statistics is as follows: Total number of instruction                  10317040 Total simulation time in cycles               4710649
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Cache performance - Leveltwoinstrcachehitlatency=6cycles

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