B-05 - /simoutorder tlb:dtlb dtlb:128:4096:2:l tlb:itlb itlb:128:4096:4:l cache:dl1 dl1:512:32:2:l cache:il1 il1:512:16:4:l cache:dl2

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./sim-outorder   –tlb:dtlb   dtlb:128:4096:2:l   –tlb:itlb   itlb:128:4096:4:l   –cache:dl1  dl1:512:32:2:l   –cache:il1   il1:512:16:4:l   –cache:dl2   dl2:1024:256:16:l   –cache:il2   dl2   – redir:sim   results/anagram5.out   –redir:prog   results/anagram6.out   tests- pisa/bin.little/anagram tests-pisa/inputs/words <tests-pisa/inputs/myinput.txt SIMULATION RESULT: The simulation output file “anagram5.out” produced a number of statistics; a summary of  the statistics is as follows: Total number of instruction                  10317040 Total simulation time in cycles               4710495 Instruction per cycle                             2.1902 Cycles per instruction                            0.4566 Il1 miss rate                                         0.0002 Dl1 miss rate                                        0.0070
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This note was uploaded on 12/20/2009 for the course ECE 466 taught by Professor Staff during the Fall '09 term at Clarkson University .

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B-05 - /simoutorder tlb:dtlb dtlb:128:4096:2:l tlb:itlb itlb:128:4096:4:l cache:dl1 dl1:512:32:2:l cache:il1 il1:512:16:4:l cache:dl2

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