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SELECTING DESIGN PARAMETERS: The “sim-outorder” simulator allows a number of memory hierarchy components to be  specified such as the level one data cache, level one instruction cache, level two data  cache, level two instruction cache, hit latency for level one data cache, hit latency for  level one instruction cache, hit latency for level two data cache, hit latency for level two  instruction cache e.t.c. DESIGN A Based on current technology and reasonable data available on the specification of  memory hierarchy components, the following specifications were proposed: Cache configuration is formatted as follows: <name>:<nset>:<bsize>:<assoc>:<repl> Each field has the following meaning, <name> Cache name <nset> Number of sets in the cache <bsize> Block size <assoc> Associativity of cache <repl> Replacement policy Cache size is the product of <nset>,<bsize> and <assoc> Level one data cache (dl1:128:64:1:l) cache size =8K  Level one instr. cache (il1:256:32:1:l) cache size = 8K Level one data cache hit latency = 1 cycle Level one instr. cache hit latency = 1 cycle Level two data cache (dl2:2048:128:8:l) cache size =2M Level two instr cache (il2:2048:128:8:l) cache size = 2M Level two data cache hit latency = 6 cycles Level two instr cache hit latency = 6 cycles  TLB data cache (32:4096:4:l) size = 512K TLB instr cache (16:4096:4:l) size = 256K Based on the above configuration, I then executed sim-outorder leaving unspecified  parameters at their default values. The code for the execution is as follows: ./sim-outorder   –cache:dl1   dl1:128:64:1:l   –cache:il1   il1:256:32:1:l   –cache:dl2  dl2:2048:128:8:l   –cache:il2   dl2   –tlb:itlb   itlb:16:4096:4:l   –tlb:dtlb   dtlb:32:4096:4:l   – redir:sim   results/anagram1.out   –redir:prog   results/anagram2.out   tests- pisa/bin.little/anagram tests-pisa/inputs/words <tests-pisa/inputs/myinput.txt

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This note was uploaded on 12/20/2009 for the course ECE 466 taught by Professor Staff during the Fall '09 term at Clarkson University .

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