1
Department of Electrical and Computer Engineering
University of Minnesota
EE 2301
Fall 2009
Introduction to Digital System Design
L. L. Kinney
Discussion III Solutions
1.
The following circuit is implemented using two halfadders circuits.
The expressions for
the two outputs of a halfadder are
S = A
⊕
B where
⊕
represents the exclusiveor function, and
C = AB.
Construct a table of combinations (truth table) for each of the circuit’s outputs, SUM and
C
o
.
A
B
S
C
A
B
S
C
X
Y
C
i
C
o
SUM
SUM = (X
⊕
Y)
⊕
C
i
C
o
= (X
⊕
Y)C
i
+ XY
X
Y
C
i
SUM
C
o
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
2.
Show that the following two gate circuits realize the same function, i.e., show that
f = g.
(a)
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(b)
f = (x + y
′
)z + x
′
yz
′
= (x + y
′
+ x
′
yz
′
)(z + x
′
yz
′
)
distributive
= (x + y
′
+ z
′
)(z + x
′
yz
′
)
uniting (twice)
= (x + y
′
+ z
′
)(z + x
′
)(z + y)(z + z
′
)
distributive
= (x + y
′
+ z
′
)(z + x
′
)(z + y)
Complementation, operation with 1
g = (x + y
′
+ z
′
)(x
′
+ z)(y + z)
3.
(a)
A NAND gate can be viewed as i) an AND followed by an inverter or as ii) an OR
preceded by inverters.
Using these two interpretations convert the circuits of problem 3
into circuits that only have NAND gates and inverters.
This is done by inserting two
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 Fall '09
 LarryKinney
 Logical conjunction, Logic gate, Department of Electrical and Computer Engineering University of Minnesota, EF Distributive Distributive

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