EE2301Dis7F09Sol (1)

EE2301Dis7F09Sol (1) - (a) f = (B + D)(B' + C)(A' + C' + D)...

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Department of Electrical and Computer Engineering University of Minnesota EE2301 Fall 2009 Introduction to Logic Design L. L. Kinney Discussion VII Solutions 10/22-10/23: Gate conversions and hazards. 1. Implement the circuit below using only NAND gates and inverters as necessary. (a) Do this by performing gate conversions on the circuit as given. (b) Do this by implementing Exclusive-or using four 2-input NANDs. f x1 x2 x3 x5 x4 (a) f x5 x4 x1' x3' x2'
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(b) f x1' x3' x2' x4 x5 2. Implement the circuit above using only NOR gates and inverters as necessary. (a) Do this by performing gate conversions on the circuit as given. (b) Do this by implementing Exclusive-NOR using four 2-input NORs. (a) f x5 x4 x1 x2 x3 (b) f x4 x5 x1 x2 x3
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3. Consider the following two-level NAND-AND circuit: B' D' B C' A D' f C (a) Find all hazards in this circuit. (b) Redesign the circuit as a two-level NAND-AND circuit that is free of all hazards.
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Unformatted text preview: (a) f = (B + D)(B' + C)(A' + C' + D) f A B C D 00 01 11 10 00 01 11 10 Static-0 hazards: (0000) (0100), (1000) (1100), (1100) (1110) (b) f = (B + D)(B' + C)(C + D)(A' + D) is hazard free. D' C' f A D' B' D' B C' 4. Find all hazards in the three-level circuit below. ( f = (BC + B'D)(A' + C' + D) = A'BC + BCC' + BCD + B'D f A B C D 00 01 11 10 00 01 11 10 1 1 1 1 1 1 1 Static-1 hazards: (0011) (0111), (1111) (1011) Static-0 hazard: (1100) (1110) Dynamic hazards: None (C only has two paths through the circuit.) Alternative solution: f = (BC + B'D)(A' + C' + D) = (B + B')(B + D)(B' + C)(C + D)(A' + C' + D) f A B C D 00 01 11 10 00 01 11 10 Static-0 hazard: (1100) (1110) Static-1 hazards: (0011) (0111), (1111) (1011) Dynamic hazards: None (B only has two paths through the circuit.)...
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EE2301Dis7F09Sol (1) - (a) f = (B + D)(B' + C)(A' + C' + D)...

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