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EE2301Dis8F09Sol

# EE2301Dis8F09Sol - Department of Electrical and Computer...

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1 Department of Electrical and Computer Engineering University of Minnesota EE2301 Fall 2009 Introduction to Digital Systems Design L. L. Kinney Discussion VIII Solutions 11/5-6: Flip-flops. 1. The J and K inputs to a JK master-slave flip-flop cannot change at arbitrary times and still operate according to the transition (state) table specified for it. Analyze the JK master-slave flip-flop implemented with NAND gates by construct a timing diagram showing the changes in P and Q resulting from the sequence of changes listed. In each case note the final value of Q. (a) Initially J = K = P = Q = C = 0 (i) JK change to 11 (ii) C changes to 1 and then back to 0 (iii) JK change to 01 (iv) C changes to 1 and then back to 0 (v) JK change 10 (vi) C changes to 1 and then back to 0

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2 (b) Initially J = K = P = Q = C = 0 (i) J changes to 1 (ii) C changes to 1 (iii) J changes to 0 (iv) K changes to 1 (v) K changes to 0 (vi) C changes 0 (c) Initially J = K = P = Q = C = 0 (i) C changes to 1 (ii) J changes to 1 (iii) J changes to 0 (iv) C changes to 0
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