EE2301Dis11F09Sol

EE2301Dis11F09Sol - Department of Electrical and Computer...

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1 Department of Electrical and Computer Engineering University of Minnesota EE2301 Fall 2009 Introduction to Digital Systems Design L. L. Kinney Discussion XI Solutions 12/3-4: Arithmetic Circuits and Controllers. 1. Make the following modifications to the serial adder of Section 18.1 in the Roth text. (a) Modify the serial adder of Figure 18-1 and the controller state graph of Figure 18-3 to assure that the first carry, C 0 , into the adder is 0. Do this by forcing the output of the carry FF to be 0 during the first shift. (The carry FF does not have a clear or set input.) (b) Assume the carry FF has an asynchronous clear input. Redo Part (a) using the asynchronous clear to force C 0 to be 0. (c) Add an overflow, ov, output signal to the circuit and any necessary circuitry. Assume the numbers are unsigned numbers. When is the signal on ov valid? (d) Repeat Part (c) assuming the numbers are two’s complement numbers. (e) Assume the shift registers have a parallel load capability with control signal PL. The augend and addend are available on parallel inputs during the clock cycle when the start signal, St, becomes 1. Modify the controller state graph of Figure 18-3 so that
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This note was uploaded on 12/20/2009 for the course EE 2301 taught by Professor Larrykinney during the Fall '09 term at Minnesota.

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EE2301Dis11F09Sol - Department of Electrical and Computer...

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