EE2301EX2F08Sol

EE2301EX2F08Sol - University of Minnesota Department of...

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University of Minnesota Department of Electrical and Computer Engineering EE2301 Fall 2008 Introduction to Digital System Design L. L. Kinney Exam II (Closed Book) Solutions 1(20) Mark each of the following statements as either T (true), F (false) or leave blank. A correct T or F answer receives 2 points, an incorrect T or F answer receives –2 points, and a blank answer receives 0 points. __F__ (a) A 5-variable function can always be realized using a 8-to-1 MUX without any additional gates assuming the inputs are available in both true and complement form. __T__ (b) A well-behaved asynchronous sequential circuit must have at least one stable state for each input combination. __T__ (c) The asynchronous inputs to a positive, edge-triggered, clocked flip-flop can cause the state of the flip-flop to change at any time during the clock cycle. __F__ (d) In VHDL signal assignment statements are executed sequential in the order they are listed in the program. __T__ (e) The D input to a D-type, master-slave flip-flop can contain glitches while the clock is high provided that it is stable around the negative edge of the clock. (The master stage is enabled while the clock is high.)
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This note was uploaded on 12/20/2009 for the course EE 2301 taught by Professor Larrykinney during the Fall '09 term at Minnesota.

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EE2301EX2F08Sol - University of Minnesota Department of...

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