EE2301HW7F09Sol

# EE2301HW7F09Sol - Department of Electrical and Computer...

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1 Department of Electrical and Computer Engineering University of Minnesota EE2301 Fall 2009 Introduction to Digital System Design L. L. Kinney Problem Set VII Solutions Due Thurs. Nov. 12, 2009 prior to the beginning or immediately after class. Please put your EE 0301 Discussion Section number (1, 2, 3, 4 or 5) ( not your EE 2301 Laboratory Section number) on your homework. 1. You are given a positive edge-triggered D flip-flop with t s,min = 20 ns and t h,min = 5 ns. (a) Construct the circuit for a positive edge-triggered SR FF using the D FF and a minimum number of NOR gates and inversters. If the inverters and the NOR gates have a maximum propagation delay of 15 ns and a minimum propagation delay of 2 ns, what are t s,min and t h,min for the SR FF. (b) Repeat part (a) for a positive edge-triggered JK flip-flop. (a) The transition table for an SR FF is Present Next State State Q SR = 00 SR = 01 SR = 11 SR = 10 0 0 0 1 1 1 0 1 Q + = S+R Q = R (S + Q) The following circuit is derived from the POS equation S R Clk Q Q' D Clk The maximum propagation delay through the logic is 30 ns; a change on S must reach D

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EE2301HW7F09Sol - Department of Electrical and Computer...

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