EE2301HW9F09Sol

# EE2301HW9F09Sol - Department of Electrical and Computer Engineering University of Minnesota EE2301 Introduction to Digital System Design Problem

This preview shows pages 1–3. Sign up to view the full content.

1 Department of Electrical and Computer Engineering University of Minnesota EE2301 Fall 2009 Introduction to Digital System Design L. L. Kinney Problem Set IX Solutions Due Thurs. Dec. 3, 2009 prior to the beginning or immediately after class. Please put your EE 0301 Discussion Section number (1, 2, 3, 4 or 5) ( not your EE 2301 Laboratory Section number) on your homework. 1. Problem 12.25 in the text. Q 3 Q 2 Q 1 Q 0 Clr Ld 0000 1 0 0001 1 0 0010 1 0 0011 1 0 0100 1 1 0101 x x 0110 x x 0111 x x 1000 x x 1001 x x 1010 x x 1011 1 0 1100 1 0 1101 1 0 1110 1 0 1111 1 0 For state 1111, either Increment, Clear or Parallel Load may be used. Increment results in the simplest equations, then Clr = 1 , Ld = Q 3 Q 2 , P 3 = 1, P 2 = 0, P 1 = 1, P 0 = 1. 2. Problem 12.26 in the text. (a)

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
2 011 111 110 100 010 101 001 000 (b) S in = Q 2 Q 3 or S in = Q 0 Q 3 (c) The state 0000 can only be inserted between states 0001 and 1000. For the S in = Q 2 Q 3 case the Karnaugh map for S in is S in Q 0 Q 1 Q 2 Q 3 00 01 11 10 00 01 11 10 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 S in = Q 2 Q 3 + Q 0 Q 2 Q 3 + Q 1 Q 2 Q 3 + Q 0 Q 1 Q 3 .
This is the end of the preview. Sign up to access the rest of the document.

## This note was uploaded on 12/20/2009 for the course EE 2301 taught by Professor Larrykinney during the Fall '09 term at Minnesota.

### Page1 / 6

EE2301HW9F09Sol - Department of Electrical and Computer Engineering University of Minnesota EE2301 Introduction to Digital System Design Problem

This preview shows document pages 1 - 3. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online