Lecture07 - ENGRD 2300 Introduction to Digital Logic Design...

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Lecture 7: 1 ENGRD 2300 Introduction to Digital Logic Design Timing and Hazards Documentation Standards Fall 2009
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Lecture 7: 2 Announcements Review Ch 1, Ch 3.1-3.3, Ch 4.1-4.4, Ch 6.1-6.3 Read 6.3 – 6.9 But don’t worry about the HDL (ABEL, VHDL, Verilog, etc) stuff HW2 due Wed, Sept 23 at 1:35pm Posted to Blackboard Fun with K-maps! Lab 3 prelab 3 due Fri, Sept 18 at 1:35pm Lab 4 ?
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Lecture 7: 3 Real-World Logic Design Lots more than 6 inputs – can’t use Karnaugh maps Design correctness more important than gate minimization Use “higher-level language” to specify logic operations Use sophisticated programs to manipulate logic expressions and to minimize logic PALASM, ABEL, CUPL – developed for PLDs VHDL, Verilog – developed for ASICs
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Lecture 7: 4 Propagation Delay Time for change at input to cause change at output t pHL measures High to Low delay t pLH measures Low to High delay Typically specified between 50% points
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Lecture 7: 5 Timing Diagram Shows how outputs respond to changes in inputs over time
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Lecture 7: 6 X Y Z Z•Y X•Z’ F X Y Z Z’ X•Z’ Z•Y F Timing Diagram t p of AND gate
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Lecture 7: 7 Timing Behavior of Combinational Networks Thus far, we’ve assumed steady state (static) inputs to our logic function We need to be concerned with the dynamic behavior of our circuit when the inputs change (0 1, 1 0) Timing analysis involves characterizing dynamic circuit behavior to ensure the circuit meets timing specifications under all possible conditions
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Lecture 7: 8 Timing Specifications
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Lecture07 - ENGRD 2300 Introduction to Digital Logic Design...

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