Lecture08

Lecture08 - ENGRD 2300 ENGRD 2300 Introduction to Digital...

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ENGRD 2300 Introduction to Digital Logic Design SI Components Fall 2009 MSI Components XOR Gates ultiplexers Multiplexers Demultiplexers ecoders Decoders Encoders tate Drivers Lecture 8: 1 3-State Drivers
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Announcements HW2 due Wed, Sept 23 at 1:35pm Posted to Blackboard Fun with K-maps! Lab 4 Prelab will be due Fri Oct 2! Lecture 8: 2
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Readings Chapter 1, Sections 3.1-3.3 Sections 3.4-3.7 Section 4.1 Sections 4.2 – 4.3 Sections 4.4, 6.1 – 6.2 Sections 6.4 – 6.9 (TODAY) But don’t worry about the HDL (ABEL, VHDL, Verilog, etc) stuff Sections 2.1–2.9, 6.10, 6.11 (TUESDAY) Sections 6.10.6 and 6.10.7 (THURSDAY) Lecture 8: 3
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Where are we? Transistors Î gates Î circuits Created basic Boolean logic building blocks from transistors NOT, AND, OR, NAND, NOR Using these basic logic functions, we’ll build even more complex circuits XOR, encoders, decoders, multiplexers, adders, comparators, etc. uilding blocks of most combinational circuits Lecture 8: 4 Building blocks of most combinational circuits Medium Scale Integration (MSI)
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XOR Gates Same as an OR gate, except for the case where both inputs are 1 XNOR – complemented version of XOR XY X Y (X Y)’ 00 0 1 01 1 0 10 1 0 11 0 1 MSI part 74LS86: Quad 2-input XOR Lecture 8: 5 This is not an SSI component
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XOR Gate Implementations No direct representation with a few transistors F=X•Y’+X’•Y = 0 +X•Y’+ 0 +X’•Y X ’+X ’+Y ’+X’ =X•X+X•Y+Y•Y+X •Y =X•(X’+Y’)+Y•(X’+Y’) =X•(X•Y)’+Y•(X•Y)’ Lecture 8: 6
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Routing Data in Digital Designs In digital designs, data can often come from, and go to, several places A multiplexer routes one of multiple inputs to a single output A demultiplexer routes a single input to one of ultiple outputs multiple outputs control control Lecture 8: 7 4x4 switch multiplexer demultiplexer
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Multiplexer (“mux”) Digital switch Connects data from one of n sources ( b bits wide) to il tt ( it id ) a single output ( b bits wide) Typically, n = 2, 4, 8, or 16; b = 1, 2, or 4 (in an MSI part) Select input determines which of the n sources is p connected to the output Requires log 2 n Select bits Enable input must be asserted; otherwise, no connection is made Useful when multiple data sources need to be uted to a single destination Lecture 8: 8 routed to a single destination Ex: select 1-of-n registers as input to the ALU
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General Mux Operation nable s b enable select b . b First data-input bus Second data-input bus Data- out bus b . . n th data-input bus Lecture 8: 9
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Exercise 2:1 mux Two 1-bit inputs A :1 One 1-bit output 1-bit select input Z I0 I1 2:1 mux Construct Truth Table ap K-map Minimal sum-of-products expression Lecture 8: 10
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n:1 Multiplexers 2:1 mux: Z = A' I0 + A I1 4:1 mux: Z = A' B' I0 + A' B I1 + A B' I2 + A B I3 8:1 mux: Z = A' B' C'
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This note was uploaded on 12/25/2009 for the course ECE 2300 at Cornell.

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Lecture08 - ENGRD 2300 ENGRD 2300 Introduction to Digital...

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