Lecture12 - ENGRD 2300 ENGRD 2300 Introduction to Digital...

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ENGRD 2300 Introduction to Digital Logic Design Fall 2009 Sequential Synchronous Circuit Analysis State Machines Lecture 12: 1
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Announcements Prelim 1 Tue Oct 20 Details to come Lab 4 make up If you have missed a lab due to illness, you may ake it up Wed Oct 14 between 1:25 :25pm make it up Wed Oct 14 between 1:25-4:25pm Email me if you would like to do this. ab 5 to be posted Lab 5 to be posted Prelab 5 due Friday Oct 23 A Evals Oct 7 to Oct 18 TA Evals, Oct 7 to Oct 18 Lecture 12: 2
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Readings Chapter 1, Sections 3.1-3.7 Sections 2.1–2.9 Section 4.1 – 4.4 Sections 6.1 – 6.11 Sections 7.1, 7.2 Sections 7.3 (TODAY) Section 7.4 – 7.5 (Thursday) Lecture 12: 3
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D-Type FF Recap Sets Q to value of D on rising (falling) clock edge D is a synchronous input as it only affects the state on the rising (falling) clock edge does not change between clockedges Q does not change between clockedges Also may output Q’ synchronous preset Asynchronous preset Immediately sets Q to 1 Usually active low Q D LK PRE Asynchronous clear Immediately sets Q to 0 Q CLK CLR Lecture 12: 4 Usually active low
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T Flip-Flops “Toggle” flip-flop Changes state each time T pulses Useful for counters Q T Q D Q Q Q CLK T T Q Lecture 12: 5
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T Flip-Flop Counters Q 2 Q 1 Q 0 0 0 0 0 0 1 Q T CLK Q 0 3-bit T flip-flop ounter 0 1 0 0 1 1 00 Q counter When all lower significant bits are 1 0 0 1 0 1 1 1 0 11 Q Q T Q 1 1’s Æ toggle this bit on next CLK 1 1 1 0 0 0 0 0 1 Q 2 0 1 0 0 1 1 1 0 0 Q Q T Lecture 12: 6
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T Flip-Flops with Enable Changes state only if enabled Useful for many counter functions Q Q EN T EN T Q Lecture 12: 7
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J-K Flip-Flops Q = J•Q’ + K’•Q Lecture 12: 8 A flip-flop version of an S-R latch
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Latches Have an enable signal Output follows input whenever enable asserted Output “latches” its last value when the enable signal deasserted Types S-R latch Î Set/Reset latch D latch Î Data latch Lecture 12: 9
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Flip-Flops Have a clock signal Output changes only on triggering clock edge positive edge triggered Æ rising edge of clock negative edge triggered Æ falling edge of clock Types D flip-flop Î input captured on the output flip op utput flips between 0 and 1 on each T flip-flop Î output flips between 0 and 1 on each triggering clock edge Useful for counters Lecture 12:10
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Data Latches and Data Registers Data latch Larger quantity of data (e.g., byte) can be held in a lti it d t l t h multi-bit data latch Multiple D latches
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Lecture12 - ENGRD 2300 ENGRD 2300 Introduction to Digital...

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