lab7 - ENGRD 2300: Introduction to Digital Logic Design Lab...

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ENGRD 2300: Introduction to Digital Logic Design Fall 2009 Lab 7 Single Cycle Microprocessor Lab 7. Single Cycle Microprocessor You will not turn in a formal prelab for this lab; instead you will turn a postlab after your lab session. However, you must complete your design before your lab section meets, otherwise you may not be able to complete the required lab session. The Lab portion is to be completed during your lab section the week of November 30, 2009. Final reports are due Saturday December 5. Reports are due at 1:25pm in the drop box for your section. Postlabs are also due Friday, December 4 at 1:25pm via CMS. Part I: Prelab For this lab, you may choose a lab partner from your section and do the pre-lab as a team. This is a more involved pre-lab than you worked on in previous labs, so it is highly recommended that you work with a partner on the pre-lab. Be careful to choose a partner with whom you can work well and have similar work habits and make sure that the pre-lab work is split evenly between partners. Don’t forget that each partner is responsible for understanding the entire design and that you will submit individual final reports. For your convenience, a set of template files for this lab has been placed on Blackboard for you to download. The top-level design file is called lab7.bdf and contains all the inputs and outputs that you will need for this lab. This template file defines only the required inputs and outputs; you will have to provide the remaining design elements. The template files also contain a clock divider, lab7_clk.v, that can be used to slow the execution of the processor in lab. Instruction and data memory modules will also be placed on Blackboard. You will not turn in a prelab for Lab 7. You will have two lab periods during which you can debug, test and demonstrate your processor design. Introduction Your task is to design a simple single cycle microprocessor based on the design discussed in class. You will use the Cyclone II FPGA on the Altera board clocked at 50 MHz. Your processor must be able to execute the following instructions, in the R and I formats discussed in class. (You do not have to implement any J format instructions.) Instruction F OP FUNCT ADD rd,rs,rt R 1111 000 SUB rd,rs,rt R 1111 001 SRA rd,rs R 1111 010 SRL rd,rs R 1111 011 SLL rd,rs R 1111 100 AND rd,rs,rt R 1111 101 1
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ENGRD 2300: Introduction to Digital Logic Design Fall 2009 Lab 7 Single Cycle Microprocessor 2 OR rd,rs,rt R 1111 110 NOP R 0000 000 HALT R 0000 001 LB rt, imm (rs) I 0010 SB rt, imm (rs) I 0100 ADDI rt,rs, imm I 0101 ANDI rt,rs, imm I 0110 ORI rt,rs, imm I 0111 BEQ rt,rs, target I 1000 BNE rt,rs, target I 1001 BGEZ rs, target I 1010 BLTZ rs, target I 1011 For most of these instructions, you will be able to decode the instructions into the corresponding control words according to the decoding table given in class. The HALT instruction will require some additional hardware to implement. You will design all elements of the microprocessor except for the Instruction RAM and Data
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lab7 - ENGRD 2300: Introduction to Digital Logic Design Lab...

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