lab5.map - Analysis & Synthesis report for lab5...

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Unformatted text preview: Analysis & Synthesis report for lab5 Mon Oct 26 23:39:28 2009 Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition Q--------------------- ; Table of Contents ;--------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Source Files Read 5. Analysis & Synthesis Resource Usage Summary 6. Analysis & Synthesis Resource Utilization by Entity 7. Registers Removed During Synthesis 8. General Register Statistics 9. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_10MHz 10. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_1MHz 11. Parameter Settings for User Entity Instance: var_clk:inst| pclock:counter_100kHz 12. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_10kHz 13. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_1kHz 14. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_100Hz 15. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_10Hz 16. Parameter Settings for User Entity Instance: var_clk:inst|pclock:counter_1Hz 17. Port Connectivity Checks: "var_clk:inst|pclock:counter_1Hz" 18. Port Connectivity Checks: "var_clk:inst|pclock:counter_10MHz" 19. Analysis & Synthesis Messages---------------- ; Legal Notice ;---------------- Copyright (C) 1991-2009 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. a +-----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------ +----------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Mon Oct 26 23:39:28 2009 ; ; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ; ; Revision Name ; lab5 ; ; Top-level Entity Name ; lab5 ; ; Family ; Cyclone II ; ; Total logic elements ; 83 ; ; Total combinational functions ; 83 ; ; Dedicated logic registers ; 36 ; ; Total registers ; 36 ; ; Total pins ; 25 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 0 ; +------------------------------------ +----------------------------------------------+ + +--------------------------------------------------------------------------------------------------------+...
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This note was uploaded on 12/25/2009 for the course ECE 2300 at Cornell University (Engineering School).

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lab5.map - Analysis & Synthesis report for lab5...

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